By manipulating the charge profile through the inverted sidewall patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved. The fabricated memory cell has about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall patterning method under the same control gate based on damascene gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) gate length devices.

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A p-channel SONOS memory, based on band-to-band tunneling initiated avalanche hot-hole injection mechanism, was firstly proposed to solve the F-N erase problem in NAND flash application. The fabricated device with 50-nm gate length effectively suppressed the short channel effect and featured an excellent program and erase performance, where the time scale of a few and ~100 �sec could be obtained, respectively.

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