This paper presents a mathematical analysis of the effect of limited precision analog hardware for weight adaptation to be used in on-chip learning feed-forward neural networks. Easy-to-read equations and simple worst-case estimations f o r the maximum tolerable imprecision are presented. As an application of the analysis, a worst-case estimation on the minimum size of the weight storage capacitors is presented.

The design of integrated high-frequency continuous-time filters has made considerable progress in the past few years. As the signal frequencies increase the design of the integrator circuits used in most of these filters becomes more critical. To give direction to the circuit design minimum specifications for the gain and phase of the integrator circuits would be helpful. In this paper a practical method of finding these integrator specifications from the filter specifications is developed. An example of application of the method to a sixth-order chebyshev band-pass filter is given and the result is verified by computer simulation.

The results of an optimization procedure performed for a continuous wave rf excited sealed CO2 waveguide laser are presented. Parameters that affect laser performance, such as the excitation frequency, the gas pressure, and composition, as well as the electrode temperature and different kinds of circuit losses have been analyzed. An output power of 41 W (17.7 kW/ℓ) with an efficiency of 12% has been obtained from an optimized laser with an active length 37 cm.

The prmclple of measurmg pressure by means of a resonant diaphragm has been studled An oscillator conslstmg of an integrated amphfler with a plezoelectrlcally driven diaphragm m its feedback loop has been bullt The oscillator frequency 1s accurately proportional to the square of the pressure m the range 60 to 130 Torr The frequency range 1s 1324 to 1336 Hz (this range being limited by a spurious mode which could be suppressed by better processing) for a 25 mm diameter diaphragm made of a slhcon wafer and with PZT ceramics as driver and receptor We have made an mtegrated version (1 X 1 mm2) of a square resonant diaphragm pressure gauge by selective etchmg of (1 0 0) planes with ethylenedlamme The plezoelectrlc drlvmg maternal was sputtered zmc oxide A driver was deposited midway between the bending point and the point of greatest curvature A receptor was located at a symmetrlcal posltlon to give an optimum transfer condltlon The integrated current amplifier had a low impedance differential mput stage, two gam cells and a high Impedance output stage These electrical conditions ensured maximum elastic freedom of the diaphragm A dlgltal clrcult m 12L technology has been designed and made with eight-bit parallel read out of the frequency This clrcult may be directly connected to a mlcroprocessor The whole system contams the sensor chip, the analog amphfler chip and the digital chip, all m compatible technology *Based on a Paper presented at Solid-State Transducers

Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up t o 70 dimensional vectors within 50 nanoseconds. The decisionmaking process of the implemented feedforward neural network enables this type of computation to tolerate weight discretization, synapse nonlinearity, noise, and other nonideal effects. Although our prototype does not take advantage of advanced CMOS technology, and was fabricated using a 2.5-pm CMOS process, it performs 6 billion multiplications per second, with only 2W dissipation, and has as high as 1.5 Gbyte/s equivalent bandwidth.lthough neural networks offer exceptionally powerful parallel computation performance, most current applications focus on exploiting their leaming capabilities. The ability of neurai networks to learn from examples has given rise to several quite successful experiments. Those involving handwritten character recognition, speech recognition, and similar challenges in which biological systems overshadow artificial intelligence come to mind.Still, the benefits of unique parallel processing that neural networks afford warrant our attention as well. With fully parallel neural hardware, processing time is independent of the data-size the network must process. Only a few computing steps require serial processing, making computation time extremely short. The inner product computation involved does present one major challenge for realizing the hardware of neural nets. Therefore, if an application does not demand high precision, the compact, high-speed analog approach provides great advantages.Analog techniques let us create single-chip architectures of complex neural networks, featuring low cost and low power dissipation. Such hardware, offering processing times as low as several microseconds for as large as 128 dimensional input vectors, is already commercially available.' Still, solving for application domains that demand tens of nanoseconds of processing delayzt3 for similarly large input vectors is almost impossible. The new architecture this article describes provides precisely this sort of highcomputing performance, offering one solution for a number of demanding applications. Nuclear research applicationsTo help understand the behavior of fundamental particles and forces, Hamburg's High Energy Physics (HEP) Institute Deutsches Elektronen Synchrotron (DESY) operates two large detectors installed within its hadron-electron ring accelerator (HEM). They are called H1 and Zeus. The two detectors contain different components, each specialized for detecting track, momentum, or energy of particles coming from the interaction region, where electrons and protons collide.These detectors provide tremendous amounts of information through 200,000 analog channels, sampled at a rate of 10 million times a second and producing 10l6 bytes of data per second. The resulting data flow, which requires real-time processing, imposes a great challenge for the dataacquisition system, far exceeding the capabilities even of available superco...