A novel free-space coupling system combined with a multi-core fiber enables upscaling to a record space-division-multiplexed (SDM) channel number of 19. We achieve 305-Tb/s transmission over 10.

I. ABSTRACTAn advanced 0.1 p m CMOS technology on SO1 is presented. In order to minimize short channel effects, relatively thick nondelpleted (0.1 p m ) SO1 film, highly non-uniform channel doping and source-drain extension-HALO were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 p m werc obtained. Very high speeds wcre obtained: Unloaded dclay was 20 psec, and fully loaded NAND (FI=FO=3, C~= 0 . 3 pF) delay was 130 pscc at supply of 1.8 V.

I. ABSTRACTIn this paper a CMOS technology with the nominal channel length of 0.15 p m and minimum channel length below 0.1 p m is presented. Loaded NAND (FI=FO=3, Ct=240 f F ) delay of 200 psec and unloaded delay of 33 psec at supply voltage of 1.8 V is demonstrated. In order t o minimize short channel effects down to channel length below 0.1 p m , highly non-uniform channel doping obtained by indium and antimony, and source-drain extensions were utilized. To minimze the gate RC, a polycide stack gate structure was used. :[NTRODUCTION AND DESIGN POINTDeep submicron CMOS will be the main technology for ULSI systems. Figure 1 is a summary of the trend observed in CMOS scaling. As room temperature CMOS is scaled down below 0.35 p m , one is forced t o reduce the operating voltage of the MOS device due t o reliability and power constraints. Presently the state of .;he art CMOS is a 0.25 p m CMOS operating at 2.5 V [l]. Upo:n further scaling, the supply voltage should be dropped to about 1.5-2.2 V. The power supply choice depends on per-Tormance/reliability/power trade-offs. Reduced power supply allows scaling of the gate oxide within 4-5 nm range. It is estimated that for a 0.15 pm CMOS, devices with L~f f less than 0.1 p m should have acceptable threshold roll-off and off CUIrent. In this work in order t o contain the short channel effect (SCE), highly non-uniform channel doping [2], and very shallow junction/extensions were utilized. Highly non-uniform doping, allows high dopant concentration just below the channel in order to shield the drain field, and at the same time allows low device threshold (VT) and high mobility. Gate RC becomes a significant part of the circuit delay for submicron CMOS circuits. 13evices with both conventional salicide structure and a polycide structure (to reduce the resistance of the gate poly lines below 0.15 p m ) were fabricated. Figure :2 is a schematic cross section of a 0.15 p m CMOS: Both nMOS and PMOS are surface channel, twin well CMOS on p-/p+ epi. Gate oxide was 4.5 nm. E-beam lithography was used for the gate patterning in order to obtain channel lengths below 11.1 p m . Indium and antimony were used in order to obtain highly non-uniform channel implants in order to minimize SCE's. Background doping was 2-4x PROCESS TECHNOLOGYUltra-shallow extensions were obtained by pre-amorphization by indium and low energy As implant for nMOS and Sb pre-amorphization and BF2 for PMOS devices. Figure 3 is a typical profile used in nMOS and PMOS extensions and channel implants. The deep junctions is used for robust contact process. A thick spacer was formed in order to place the deep junction far from the channel. The gate stack was dual doped poly, followed by a thick sputtered Tis& and covered with dielectric to protect the polycide later in the process, or conventional salicided structure. The deep junctions were salicided t o minimize the source and drain sheet resistance. Figure 4 presents the device characteristics for 0.1 p m L~f f nMOS and PMOS. Figure 5 is the device characteristi...