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The growing demand for higher performance in the storage and access of data in various consumer electronic and computing devices has driven the development of nonvolatile memory (NVM) technologies. The promising candidates for future NVM such as FeRAM and PCM have demonstrated shorter access time, faster programming and wide read/write bandwidth in the chip and the memory macro [1][2]. Resistive memory (ReRAM) is also one of alternative NVMs, because of its low operating voltage, high speed and good scalability. Several types of ReRAM characteristics have been investigated on memory array [3][4][5][6]. However, most are limited in terms of memory array performance because of not having suitable read/write circuit for ReRAM. In this work, we present a 4Mb conductive bridge ReRAM test macro realizing 2.3GB/s read-throughput, 216MB/s program-throughput and robust reliability results by using read/write fully functional device technology with direct sense in programming (DSIP) method.The micrograph of 4Mb test macro built in a 0.18μm CMOS technology and features are shown in Fig. 11.7.1. The test macro is organized into 16 tiles of 256Kb each. Dual-layered conductive bridge elements that employ CuTe-based conductive material and GdOx thin insulators are used in 1T-1R memory cells in the same manner as previously reported elsewhere [6]. The resistive element has top and bottom electrodes and is of the bipolar switching where high resistance state (HRS) turns into low resistance state (LRS) when the top electrode is positively biased and reversely when the bottom electrode is positively biased. The top electrodes form a plate covering a half of the tile. Bringing HRS into LRS is defined as "erase" assuming that the operation involving driving the large top electrode is done by blocks. The opposite is defined as "program" done by individual bits.The memory cell and circuit diagram are shown in Fig. 11.7.2. Each tile has 64 write drivers and sense amplifiers in the middle of the folded arrangement of BLs. All of the 1024 (64 per tile) sense amplifiers are activated simultaneously in read operation and the 128 (8 per tile) write drivers are activated simultaneously in program operation. Figure 11.7.3 shows schematic of the sense amplifier, reference cell and write driver. In read operation, the Vo pair is compared while the BLs are maintained by VBIAS at low read voltages to prevent destruction of data. In program operation, the program pulse length and height are controlled by WRTEN and VGRST, respectively. For the verify functionality that is implemented in program operation, DSIPEN activates DSIP circuits, which is described in the latter part. BLEQ provides equalization control for fast and accurate sensing results.One of the most common challenges in realizing ReRAM is to support a sufficient read speed. Though applications demand high performances in readthroughput, a lot of issues have to be addressed to sense a huge number of cell resistances within a very limited time in a robust manner. Our solution includes the...