No abstract

Soldering on ball grid arrays (BGAs) and dense circuit features is standard practice in the microelectronics industry. Key to the success of this operation is solder joint reliability (SJR). The evaluation of solder joint reliability can be satisfied by high speed shear testing (HSS). HSS testing in combination with representative test vehicles are tools that can be used to gain statistical data in order to evaluate the impact of controlled testing. During such a round of controlled testing in the context of a palladium phosphor ENEPIG process, it was observed that the palladium initiation speed and IMC may be related to HSS results. The focus of this paper is not targeting all the optimizations that can lead to high end reliability performance for solderability. This paper will strive to convey steps that are available to all fabricators to maximize High Speed Shear results (HSS). In this paper, it will be shown that soldermask related pinholes can be overcome by implementing a reduction assisted immersion gold bath. This section will also culminate in SJR improvements and stability. The prevention of pin holes is a complicated multifaceted problem. This paper will address the notion that, if pinholes are evident, an enhanced immersion gold bath can be used to overcome serious corrosion. Disturbances in the nickel deposit can be weaknesses that are open for unusual locally aggressive atom exchange between the gold and the nickel that will result is hyper-corrosion. A reduction assisted gold bath is able to mask such areas with controlled deposition. This paper will demonstrate the effectiveness of the optimized, purpose designed, gold bath in overcoming pinhole related corrosion whilst simultaneously scrutinizing the ability of the reduction assisted gold bath to maintain or enhance the reliability expectations that are benchmarked by traditional immersion gold alternatives. During studies it has also been observed that processing is also instrumental in assuring maximum soldering reliability. Whilst rinsing is an accepted procedure, the degree and method of rinsing is often a controversial topic. This is especially true of vertical processes where fluid exchange is replaced by soaking, or in other words agitation neutral, volume related dilution. Environmentally aware practices err on the side of minimal water consumption. This is a requirement that is influenced or selectively amplified by geographical locations. This technical paper will demonstrate that the palladium initiation is crucial if maximum SJR is to be achieved. This experience was gained in association with a significant OEM. Electrochemical and advanced optical techniques will be used to demonstrate that the SJR in terms of HSS can be correlated to palladium initiation and resultant IMC formations. In summary process adjustments can be employed to improve soldering performance and repetition. An optimized reduction assisted gold bath will come together with processing optimizations to provide a data driven overview to convince fabricators that enhancements to their everyday processes exist and can be implemented by drop in solutions. The data that is included should be as interesting to the automotive industry as it is to the emerging substrate like panel industry (SLP).

No abstract

No abstract

System-On-Package (SOP) is a highly integrated systems packaging technology for convergent computing, communication, consumer, and bio-electronic functions in a single package or module. SOP aims to miniaturize systems by the integration of system-level components at microscale in the short term and nanoscale in the future. A key challenge for active and passive component integration is the demand for additional fine pitch wiring in the substrate for interconnecting these thin film embedded components. This adds to the already escalating need for high wiring density substrates driven by transistor density on the IC (Moore's Law). This paper addresses a critical process technology for SOP/microprocessor ultra-high density organic build-up substrates, namely, surface treatment of copper and dielectric in multilayer wiring. This process is critical for the challenges of processing and maintaining signal integrity at lines and spaces below 12ptm. A complete description of fine line and space fabrication and a novel copper adhesion process and its operating parameters are presented. We demonstrate this process with superior bonding strength through accelerated reliability testing. Results are shown not only state-of-the-art build-up films but also for highperformance substrates and prepregs in comparison to more traditional copper roughening treatment methods.