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Memory power consumption has become a big concern in server platforms. A recently proposed mini-rank architecture reduces the memory power consumption by breaking each DRAM rank into multiple narrow mini-ranks and activating fewer devices for each request. However, its fixed and uniform configuration may degrade performance significantly or lose power saving opportunities on some workloads. We propose a heterogeneous mini-rank design that sets the nearoptimal configuration for each workload based on its memory access behavior and its memory bandwidth requirement. Compared with the original, homogeneous mini-rank design, the heterogeneous mini-rank design can balance between the performance and power saving and avoid large performance loss. For instance, for multiprogramming workloads with SPEC2000 application running on a quad-core system with two-channel DDR3-1066 memory, on average, the heterogeneous mini-rank can reduce the memory power by 53.1% (up to 60.8%) with the performance loss of 4.6% (up to 11.1%), compared with a conventional memory system. In comparison, the x32 homogeneous mini-rank can only save memory power by up to 29.8%; and the x8 homogeneous mini-rank will cause performance loss by up to 22.8%. Compared with x16 homogeneous mini-rank configuration, it can further reduce the EDP (energy-delay product) by up to 15.5% (10.0% on average).

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With the fast improvement on memory bandwidth and capacity, the memory power consumption has become a major contributor to the overall system power profile. Due to the increasing importance of memory-level parallelism at the multi-core era, most memory scheduling schemes eagerly exploit such parallelism to optimize performance. A common policy used by memory controllers today is, whenever possible, always trying to open memory banks for pending requests to maximize bank-level parallelism and throughput. However, we find that this is neither power optimal nor necessary for maintaining performance because usually many banks are open while waiting for the data bus ownership.To address this issue, we propose a "Conservative Row Activation" scheme that delays the row activation operation of a request to an idle rank until its corresponding column access will not be blocked by the busy data bus. This can reduce the memory power with negligible performance impact by allowing a rank to stay at the low-power mode longer. To minimize performance impact, our scheme monitors the data bus transactions and reserves bus slots for column commands at the earliest possible time. The detailed simulation results indicate that our scheme can reduce the memory power consumption of a group of quad-core multiprogramming memory-intensive workloads with SPEC2006 applications by 5.6% on average. It may even improve the performance slightly (by 0.3% on average), because the data bus utilization can be improved by giving column accesses higher priority than other commands.

Based on the feature of vibration signal of rotating machinery in speed fluctuation processes which are combined by many modulated signals and the fault characteristic frequency of it is varied following the rotating speed, and in order to suppress the phenomenon of mode mixing, a new method combined Order Tracking analysis with Ensemble Empirical Mode Decomposition(EEMD) algorithm were proposed. First of all, the time domain vibration signal were resample and transformed into angle domain stationary signal by using the Order Tracking technique,and then, the resample signal in angle domain is decomposed into several Intrinsic Mode Function components self-adaptively with EEMD. Finally, the envelope demodulation analysis is used to deal with high order components in angle domain and the fault features can be obtained. The analysis results from the simulation and experimental signals of out-race fault in rolling bearing fully proved the effectiveness of the proposed method.