Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture

Abstract

Memory power consumption has become a big concern in server platforms. A recently proposed mini-rank architecture reduces the memory power consumption by breaking each DRAM rank into multiple narrow mini-ranks and activating fewer devices for each request. However, its fixed and uniform configuration may degrade performance significantly or lose power saving opportunities on some workloads. We propose a heterogeneous mini-rank design that sets the nearoptimal configuration for each workload based on its memory access behavior and its memory bandwidth requirement. Compared with the original, homogeneous mini-rank design, the heterogeneous mini-rank design can balance between the performance and power saving and avoid large performance loss. For instance, for multiprogramming workloads with SPEC2000 application running on a quad-core system with two-channel DDR3-1066 memory, on average, the heterogeneous mini-rank can reduce the memory power by 53.1% (up to 60.8%) with the performance loss of 4.6% (up to 11.1%), compared with a conventional memory system. In comparison, the x32 homogeneous mini-rank can only save memory power by up to 29.8%; and the x8 homogeneous mini-rank will cause performance loss by up to 22.8%. Compared with x16 homogeneous mini-rank configuration, it can further reduce the EDP (energy-delay product) by up to 15.5% (10.0% on average).

A survey of architectural techniques for DRAM power management

“…Several other techniques reduce the power consumed in each DRAM access by accessing only part of DRAM in each memory access [11,54,57,[65][66][67][68]. Thus, these techniques provision activating a much smaller portion of DRAM circuit component than what is activated in conventional DRAMs.…”

“…Fang et al [66] extend mini-rank approach to heterogeneous mini-rank design which adapts the number of mini-ranks according to the memory access behavior and memory bandwidth requirement of each workload. Based on this information, for a latency-sensitive application, their technique uses a minirank configuration which does not degrade application performance; while for a latency-insensitive application, their technique uses a mini-rank configuration which achieves memory power saving.…”

MIMS: Towards a Message Interface Based Memory System

“…Each memory access would only require a part of memory devices (in the same sub-rank) to be involved. Many different approaches could be classified as sub-rank, including Rambus's Module threading [52], Multicore DIMM (MCDIMM) [20,19], and mini-rank [59,31], heterogeneous Multi-Channel [57]. Sub-rank technology could save memory power by alleviating the over-fetch problem and improve memory level parallelism (MLP).…”