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Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO 2 shows an I Dsat of 497µA/µm at V G =V D =1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And a channel orientation effect, based on a current-flow direction, is shown. Key words: all-around gate, FinFET, sub-5nm, quantum effect Introduction Silicon-based transistors are scaled down continually in order to increase a density and speed. Multi-gate FinFETs have strengths of high robustness on short-channel effects (SCEs) and superior scalability using conventional processes [1][2][3][4][5][6][7]. However, the ultimate minimum feature-sized device operating at room temperature has been expected to be 1.5nm according to Heisenberg's uncertainty principle and Shannon-von NeumannLandauer expression [8]. The fabricated sub-5nm all-around gate (AAG) FinFET is approaching to this fundamental limit. FinFET [7]. For ultimately scaled transistor, AAG FinFET is known to be the best structure to provide scalability and flexibility in device design [9]. This work primarily focuses on feasibility and scalability of sub-5nm AAG FinFET. A threshold voltage shift by quantum confinement and an effect of current-flow direction are reported.Fabrications Fig. 1 illustrates a process flow of AAG FinFET. As a starting material, (100) SOI wafers were used. 100nm silicon film was thinned down to 14nm by using thermal oxidations and HF wet etch. Dual-resist process for a fin and a gate patterning was used to define nanometer features by e-beam lithography and non-critical large-area patterns by optical lithography. After the silicon-fin etch, a sacrificial oxide was grown and removed to alleviate etching damages. Gate dielectrics were split into 1.4nm HfO 2 by atomic layer deposition and 2nm thermal SiO 2 . Reasonable characteristics of sub-5nm devices were achieved in HfO 2 group. 30nm in-situ n + poly-silicon was deposited for the gate electrode. The gate was patterned by the dual-resist process, similarly. After the gate and spacer formation, arsenic ions were implanted to form the source and drain (S/D). 1000℃ spike annealing was utilized to activate the dopants of S/D. Finally, forming gas annealing at 450℃ was applied. Metallization was skipped for iterative annealing to optimize gate-to-S/D overlap. The fabricated device dimensions are sub-5nm gate length (L G ), averaged 3nm fin width (W Fin ), and 14nm fin height (H Fin ).Results and Discussions Fig. 2 shows a SEM top-view of 3nm silicon-fin and sub-5nm gate. Fig. 3 and Fig. 4 show TEM cross-sectional views of 3nm silicon-fin (a-a' direction of Fig. 6 and Fig. 7. An on-state current is 497µA/µm at V G =V D =1.0V in Fig. 6, which is normalized by allarounded channel perime...

A novel sliding mode harmonic compensation (SMHC) scheme is proposed for the enhanced power quality in distributed generation systems under distorted grid condition. The harmonic pollution caused by non-linear loads in electrical networks brings about distorted grid voltage, power losses and heating in electrical equipments. The proposed SMHC scheme is composed of a harmonic detector and a sliding mode harmonic current controller based on the integral sliding mode control. By using the fourth order band pass filter, the proposed harmonic detector can effectively extract harmonic components without phase delay. These harmonic components can be notably suppressed by adopting the sliding mode harmonic current controller with fast dynamic response. Whereas the conventional sliding mode schemes have been developed to control the entire current value, the proposed SMHC scheme controls only the harmonic components by dividing inverter voltage model into the fundamental and harmonic models. Since the fundamental component in charge of power flow is controlled by proportional-integral controller, the chattering can be quite reduced. The proposed scheme is a non-selective harmonic compensation, which reduces the computational burden than the conventional selective schemes. The validity of the proposed scheme is demonstrated through simulations and experiments using 2 kVA laboratory prototype grid-connected inverter.

In order to alleviate the negative impacts of harmonically distorted grid conditions on inverters, this paper presents a linear quadratic regulator (LQR)-based current control design for an inductive-capacitive-inductive (LCL)-filtered grid-connected inverter. The proposed control scheme is constructed based on the internal model (IM) principle in which a full-state feedback controller is used for the purpose of stabilization and the integral terms as well as resonant terms are augmented into a control structure for the reference tracking and harmonic compensation, respectively. Additionally, the proposed scheme is implemented in the synchronous reference frame (SRF) to take advantage of the simultaneous compensation for both the negative and positive sequence harmonics by one resonant term. Since this leads to the decrease of necessary resonant terms by half, the computation effort of the controller can be reduced. With regard to the full-state feedback control approach for the LCL-filtered grid connected inverter, additional sensing devices are normally required to measure all of the system state variables. However, this causes a complexity in hardware and high implementation cost for measurement devices. To overcome this challenge, this paper presents a discrete-time current full-state observer that uses only the information from the control input, grid-side current sensor, and grid voltage sensor to estimate all of the system state variables with a high precision. Finally, an optimal linear quadratic control approach is introduced for the purpose of choosing optimal feedback gains, systematically, for both the controller and full-state observer. The simulation and experimental results are presented to prove the effectiveness and validity of the proposed control scheme.