PECVD nitride passivated high-power PHEMT's were used to study their hot carrier reliability. The typical hot carrier induced device degradation characteristics are often observed in devices with a less-than-ideal double gate recess and material layers design. With additional drain engineering work to optimize device power performance, the hot carrier effects can be alleviated drastically. However, depending on nitride deposition processes and nitride quality, Schottky diode degradation (a barrier height increase) was also observed during hot carrier stress. This study facilitates a comprehensive characterization of the hot carrier induced effects in power PHEMT's and recommends an alternative to improve the hot carrier reliability.

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Conventional wisdom suggests that in pseudomor-phic high electron mobility transistors (pHEMT's), the field between the drain and the gate determines off-state breakdown, and that the drain to gate voltage therefore sets the breakdown voltage of the device. Thus, the two terminal breakdown voltage is a widely used figure of merit, and most models for breakdown focus on the depletion region in the gate-drain gap, while altogether ignoring the source. We present extensive new measurements and simulations that demonstrate that for power pHEMT's, the electrostatic interaction of the source seriously degrades the device's gate-drain breakdown. We identify the key aspect ratio that controls the effect, L L LG G G : x x xD D D, where L L LG G G is the gate length and x x xD D D is the depletion region length on the drain. This work establishes that the design of the source must be taken into consideration in the engineering of high-power pHEMT's. Index Terms-Breakdown voltage, electric breakdown, electron tunneling, power HEMT's power MODFET's.

A systematic experiment was designed and implemented to optimize the 0.25 pm gate InGaAs/AlGaAs pseudomorphic HEMT for the fabrication of high power X-band monolithic amplifiers. The material structure and gate recess process were engineered such that the device breakdown voltage was optimized without sacrificing gain and efficiency. A two-stage high power X-band monolithic amplifier based on the optimized device has been developed. When the amplifier was operated at vds = 10 V, an output power of 9 W was achieved across the 7 to 10 GHz frequency range. A peak saturated output power of 10 W, corresponding to a power density of 1 W/mm, occurred at 8.5 GHz. When biased at 7V, the amplifier generated a peak power of 6.7 W with an associated power added efficiency of 40% at 8.5 GHz.

The programmability of FPGA suits the constantly changing convolutional neural network (CNN). However, several challenges arise when the previous FPGA-based accelerators update CNN. Firstly, although the model of RepVGG can balance accuracy and speed, it solely supports two types of kernels. Meanwhile, 8-bit integer-only quantization of PyTorch which can support various CNNs is seldom successfully supported by the FPGA-based accelerators. In addition, Winograd F(4 × 4, 3 × 3) uses less multiplication, but its transformation matrix contains irregular decimals, which could lead to accuracy problems. To tackle these issues, this paper proposes High-accuracy Branch-fused CNN Accelerator (HBCA): a toolchain and corresponding FPGA-based accelerator. The toolchain proposes inception-based branch–fused technique, which can support more types of kernels. Meanwhile, the accelerator proposes Winograd-quantization dual decimal–fuse techniques to balance accuracy and speed. In addition, this accelerator supports multi-types of kernels and proposes Winograd decomposed-part reuse, multi-mode BRAM & DSP and data reuse to increase power efficiency. Experiments show that HBCA is capable of supporting seven CNNs with different types of kernels and more branches. The accuracy loss is within 0.1% when compared to the quantized model. Furthermore, the power efficiency (GOPS/W) of Inception, ResNet and VGG is up to 226.6, 188.1 and 197.7, which are better than other FPGA-based CNN accelerators.