For efficient hardware implementation of QC-LDPC encoders, four types of rotate-left-accumulator (RLA) circuits are proposed. Although the performance of a type I RLA circuit is exactly identical to the most widely used shift-register-adder-accumulator (SRAA) circuit, its reasonable structure can derive the other three counterparts. Both type II and III RLA circuits are highly area efficient, and have the same speed as the SRAA circuit. Compared with these serial-in circuits, the parallel-in type IV RLA circuit is faster at the cost of more memory, and suitable for applications where generator matrices have fewer block rows or special parity-check matrices are used to encode.

An efficient encoding method is proposed for a class of quasi-cyclic low-density parity-check (QC-LDPC) codes with a multiple-diagonal parity-check structure. Its easy implementation with Chinese digital terrestrial/television multimedia broadcasting standard as an example is discussed. It is shown that the proposed encoder runs significantly faster and requires much fewer resources than the conventional shiftregister-adder-accumulator encoder.

This paper presents a new prime factor algorithm (PFA) for non-power-of-two point FFT. Compared with the conventional prime factor decomposition algorithms, the approach performs the in-place, in-order algorithm of the small factor DFT, and gets the in-order output finally by reading the results with the address generated by an easy and simple modular adder. It is a general purpose algorithm for variable size FFT/IFFT, which is more suitable for implementation in programmable logic device because of its regular and simple structure. As an example, this paper implements a 3780-point FFT processor for Chinese Digital Terrestrial Multimedia/Television Broadcasting (DTMB) standard, which combines the Winograd Fourier transform algorithm (WFTA) and the mixed-radix algorithm.

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