A novel overall in-place in-order prime factor FFT algorithm

Jiang, Lanxiang; Liu, Chang-yin; Zhang, Peng

doi:10.1109/cisp.2012.6469906

Cited by 6 publications

(4 citation statements)

References 8 publications

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“…The proposed 1024-point feed-forward radix-2 2 FFT core with two parallel data paths is designed using 65nm low power CMOS standard cells and the FFT processor occupies an area of 3.6 mm 2 (2.0 × 1.8 mm). To obtain the optimum supply voltage, a chain of 64 inverters is used to simulate with HSPICE [18][19][20] for investigating the relationship between supply voltage versus energy consumption as well as versus circuit delay.…”

Section: Resultsmentioning

confidence: 99%

“…Since 1960, many research works have been carried out to calculate the Fourier transform at improved speed and contributed to the Fast Fourier transform (FFT). Various FFT algorithms have been reported such as Cooley-Tukey [1], Prime-factor [2], Bruun [3], and Hexagonal [4] FFTs. Cooley-Tukey is the most commonly used FFT algorithm, which recursively breaks a discrete time series into smaller transformations to reduce the number of operations in the FT calculation at each stage.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, we present a novel FFT architecture called Radix-2 2 feed-forward multiple path delay commutator (R2 2 FFMDC) to enhance the throughput of the previous MDC topologies and reduce energy consumption by utilizing Radix-2 2 algorithm. The proposed FFT processor achieves the maximum throughput of 1.2 Gsample/s at 600 MHz and 1 V supply.…”

Section: Introductionmentioning

confidence: 99%

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An Area Efficient 1024-Point Low Power Radix-2² FFT Processor With Feed-Forward Multiple Delay Commutators

Kim

2018

IEEE Trans. Circuits Syst. I

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Radix-2 k delay feed-back and Radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel Radix-2 2 multiple delay commutator architecture utilizing the advantages of the Radix-2 2 algorithm such as simple butterflies and less memory requirement. Therefore, it is more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data paths. Here, we propose an improved input scheduling algorithm based upon memory to eliminate energy required to shift data along the delay lines. A 1024-point FFT processor with two parallel data paths is implemented in 65 nm CMOS process technology. The FFT processor occupies an area of 3.6 mm 2 , successfully operates in the supply voltage range from 0.4 V -1 V and the maximum clock frequency of 600 MHz. For low voltage, high performance applications, the processor is able to operate at 400 MHz and consumes 60.3 mW or 77.2 nJ/FFT generating 800 Msamples/s at 0.6 V supply.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Area Efficient 1024-Point Low Power Radix-2² FFT Processor With Feed-Forward Multiple Delay Commutators

Kim

2018

IEEE Trans. Circuits Syst. I

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“…The different algorithms for FFT are Hexagonal [1], Cooley-Tukey [2], Prime-factor [3] and Bruun [4]. To reduce the amount of operations within the Fourier Transform calculation at each stage Cooley-Tukey is that the popular FFT algorithm, which recursively breaks a discrete time series into smaller.…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

Padma¹

2021

TURCOMAT

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There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butterfly structures for the reduction of complex multipliers presented. Implementations of 32 bit floating point multiplier and floating point adder are presented by using single precision and compare the synthesis results with conventional system. In order to reduce the error we used floating point arithmetic for the butterfly structure. Energy efficient multiplier based on modified booth algorithm is used in radix-2 butterflies. By adopting this architecture the FFT/IFFT implementation using Xilinx FPGA Vertex-7 will improve the 25% logic utilization and the reduction in space utilization. Using arithmetic reduction the power delay product for radix 2 butterfly is reduced by 2.5% compared to normal implementation.

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Area Efficient and High-Throughput Radix-4 1024-Point FFT Processor for DSP Applications

Thokala¹

2022

Lecture Notes in Electrical Engineering

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A novel overall in-place in-order prime factor FFT algorithm

Cited by 6 publications

References 8 publications

An Area Efficient 1024-Point Low Power Radix-2² FFT Processor With Feed-Forward Multiple Delay Commutators

An Area Efficient 1024-Point Low Power Radix-2² FFT Processor With Feed-Forward Multiple Delay Commutators

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

Area Efficient and High-Throughput Radix-4 1024-Point FFT Processor for DSP Applications

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A novel overall in-place in-order prime factor FFT algorithm

Cited by 6 publications

References 8 publications

An Area Efficient 1024-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators

An Area Efficient 1024-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

Area Efficient and High-Throughput Radix-4 1024-Point FFT Processor for DSP Applications

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An Area Efficient 1024-Point Low Power Radix-2² FFT Processor With Feed-Forward Multiple Delay Commutators

An Area Efficient 1024-Point Low Power Radix-2² FFT Processor With Feed-Forward Multiple Delay Commutators