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DTM is an optical network with bandwidth reservation and support for dynamic reallocation of bandwidth. DTM is designed for real-time multimedia applications and for high-speed computer communication. DTM provides a service with real-time guarantees: it allows reservation of bandwidth, and has constant delay between two nodes. DTM uses a novel medium-access technique and provides a multicast channel service. This paper describes how resources are reserved in DTM, and describes a DTM prototype implementation to demonstrate that the protocols can be implemented efficiently.

We describe the design and implementation of a packetswitched fiber optic interconnect prototype with a ShuffleNet topology, intended for use in shared-memory multiprocessors. Coupled with existing latency-hiding mechanisms, it can reduce latency to remote memory locations. Nodes use deflection routing to resolve contention. Each node contains a processor, memory, photonic switch, and packet routing processor. Payload remains in optical form from source to final destination. Each host processor is a commercial workstt ion with FIFO interfaces between its bus and the photonic switch. A global clock is distributed optically to each node to minimize skew. Component coats and network performance figures are presented for various node configurations including bit-per-wavelength and fiber-parallel packet formats. Our efforts to implement and test a practical interconnect including real host computers distinguishes our work from previous theoretical and experiment al work. We summarize obstacles we encountered and discuss future work.

We describe the design and implementation of a packet-switched fiber optic interconnect prototype with a ShuffleNet topology, intended for use in shared-memory multiprocessors. Coupled with existing latency-hiding mechanisms, it can reduce latency to remote memory locations. Nodes use deflection routing to resolve contention. Each node contains a processor, memory, photonic switch, and packet routing processor. Payload remains in optical form from source to final destination. Each host processor is a commercial workstation with FIFO interfaces between its bus and the photonic switch. A global clock is distributed optically to each node to minimize skew. Component costs and network performance figures are presented for various node configurations including bit-per-wavelength and fiber-parallel packet formats. Our efforts to implement and test a practical interconnect including real host computers distinguishes our work from previous theoretical and experimental work. We summarize obstacles we encountered and discuss future work.

No abstract