This paper describes a motion estimation co-processor architecture that explicitly separates the implementation stages consisting of data access to the search window and the evaluation of the matching criterion from the implementation of the search strategy. The architecture is modular and can be re-configured according to the different MPEG video coding profiles and level parameters. Although the architectural solutions described here can be in principle applied to any SoC implementation technologies, the solution presented here is expressly conceived and validated on FPGA coprocessing architectures supporting mixed SW/HW implementations of video encoders such as generic PC platforms with a standard PCMCIA FPGA cards. The module has been developed in the framework of the MPEG reference hardware description activity.

Pre-fetching in a memory hierarchy is known to alleviate the "memory wall" paradigm but its use is impeded because of the difficulty to estimate efficiency when used in a complex system such as a SoC (System on Chip) or NoC (Network on Chip). Therefore, some methods are needed to evaluate the benefit of pre-fetching at the earliest possible stage in a design flow to help the designer choose architectural parameters or transform the application algorithm.In this paper we show that the emulation platform implementing the nD-AP Cache (n-Dimensional Adaptive and Predictive Cache) allows to perform a platformindependent measurement of this cache efficiency. The nD-AP Cache performs pre-fetching in multidimensional arrays which are commonly used in image processing and multimedia applications. The obtained metric can be used to extrapolate the cache performance in a much broader system configuration. The method to compute this metric is the calibration process .The performed benchmarks show that the calibration process is confident. Also, we measured that the nD-AP Cache is two times faster than a standard PowerPC 2-way set associative cache in the context of an image processing kernel.

International audienceTechnology evolution gives an easy access to high performance dedicated computing machines using, for example, GPUs or FPGAS. When designing algorithms dealing with highly structured multidimensional data, the real bottleneck is often linked to memory access. The strategies implemented in standard CPU cache architectures are no longer efficient due to the parallelism level and the inherent structure of data. This article presents the so-called "n-Dimensional Adaptive and Predictive Cache" (nD-AP Cache) architecture aiming at efficient data access for grid traversal. A theoretical model of the 3D version of the cache was setup in order to predict the cache efficiency for given statistical characteristics of the access sequences and for given parameters of the cache. The practical example of ray shooting algorithms has been chosen in order to carefully explore the design space and exercise the 3D-AP cache. For this purpose, a simulation model as well as a fully functional emulation platform have been designed. Thanks to the proven efficiency of the architecture further improvement and applications of the nD-AP Cache are discussed. Comparisons with standard caches show that the nD-AP Cache allows to be two times more efficient than an "ideal" associative cache and, this, with four times less memory

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