The flicker noise characteristics of strained-Si nMOS-FETs are significantly dependent on the gate oxide formation. At high temperature (900 C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700 C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.

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The superior transport property of Ge can reach high performance target in the future CMOS technology. However, the cost and insufficient abundance of Ge in earth make it difficult to replace Si as industry mainstream. Recently, the dual channel (ε-Si & ε-Ge) [1] and Ge epi [2] on relaxed SiGe buffer structures can have significant electron and hole mobility enhancements, but suffer the disadvantages of threading dislocation defect, rough surface, and high cost. The ultra thin Ge epitaxially grown on Si with compressive strain has the advantages of high mobility, very low cost and compatibility with CMOS process. The epi-Ge channel needs to be thick enough for carrier transport and as thin as possible to keep Ge strained. In this work, we investigate and optimize the channel design of Ge/Si heterojunction PMOS.The epi-Ge (~4nm) is directly grown on Si (100) at 525°C by UHV/CVD, and a nominal ~3nm Si-cap is grown in-situ on the top of Ge for passivation. The gate stack consists of ~300nm LTO (700°C, TEOS) as gate dielectric and a poly gate with P implantation. The one-mask process was used to fabricate FETs. Then, Pt was deposited by E-gun system and annealed in the forming gas at 420°C for 1 hr to form Schottky Barrier (SB) S/D [3]. The implanted S/D PFET is also fabricated to compare with SB S/D PFET. The TEM micrographs of the as-grown epi-Ge layer with nominal ~3nm Si-cap is shown in Fig. 1. Due to the oxidation in the air, only ~1nm Si-cap was observed by TEM ( Fig. 1(a)). The defect is observed in plane-view TEM scan with the estimated density less than 10 8 cm -2 ( Fig. 1(b)). The ~4nm epi-Ge layer is thick enough for inversion channel (Fig. 2) and thin enough to avoid full relaxation. The quantum mechanical simulation shows that the hole concentration of ε-Ge (strained Ge) PFET is confined in the Si-cap/epi-Ge heterojunction and the ε-Ge quantum well (Fig. 3), and the hole concentration of ε-Ge PFET is higher than that of the bulk Si. To improve the interface between dielectric and epi-Ge layer, Si-cap is grown on the top of Ge to passivate and smoothen the surface. The thicker Si-cap can reduce roughness, but would lead to the formation of buried channel. While, thinner Si-cap would be totally consumed in the process and yield high D it (Fig. 4). Thinner Si-cap (nominal ~1nm) yields large D it , indicating that nominal ~3nm Si-cap (~1nm after process) is essential for our device process. The D it (~1x10 11 cm -2 ·eV -1 ) of Ge PFET slightly higher than that of the bulk Si device is obtained from the high-low frequency C-V measurement. Note that due to lattice misfit, the epi-Ge/Si has the built-in compressive strain. 1.25% compressive strain was observed by the shift of Raman spectra. The partial strain relaxation of epi-Ge layer is maybe due to the dislocation, Si out-diffusion into epi-Ge, and the wavy ripple (observed in the long range TEM) [4]. The compressive strain can further enhance the hole mobility in the Ge channel. The apparent bandgap from the EL of the epi-Ge/Si MOS LED is ~1eV. The bandgap ...

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