Widespread use of lead-free solders requires precise control of the temperature on a substrate during reflow soldering, because the margin between the higher melting temperatures of lead-free solders and the heat-resistant temperatures of electronic components becomes narrow. For this purpose, the thermal simulation method has been developed for predicting the temperature on a substrate and optimizing the temperature profile during the reflow soldering process. Most reflow furnaces have two heating systems: forced convection by hot gas and radiation by infrared rays. Heat transfer by convection can be calculated with the experimental equation for multiple impinging jets without any fluid analysis. Heat transfer by radiation was calculated with a mechanical solver, taking into account the shape factor between the moving substrate on a conveyer and the heater. The predicted temperatures obtained by the simulation method showed good agreement with measured temperatures using a test substrate. Then, this simulation method was applied to mobile phone substrate in order to optimize the reflow process.

This paper reports a thin-film encapsulation technology for wafer level micro-electro-mechanical systems (MEMS) package, using poly-benzo-oxazole (PBO) sacrificial material and plasma enhanced chemical vapor deposited silicon oxide (PECVD SiO) cap layer. This technique, which is applicable for MEMS technologies, saves die size and enables conventional package processes such as dicing, picking, mounting and bonding. Besides the fabrication processes of the thin-film encapsulation, this paper also presents the results of finite element models (FEMs) for the deflection and the mechanical stress of the thin-film caps.Moreover, in order to mount a MEMS chip with the thinfilm capsulations and another integrated circuit (IC) chip that controls a MEMS chip in the same package, we have also developed an epoxy reinforcement technique for protecting the thin-film encapsulations and a topography wafer thinning technique for the MEMS chip. And then the system in package (SiP) for the MEMS and IC chips is fabricated successfully based on the mechanical analysis of the SiP process. IntroductionSince MEMS, such as various sensors and radio frequency (RF) actuators [1], [2], consist of movable parts and need to be operated in vacuum or controlled atmosphere, the conventional package techniques for large-scale integrated circuits (LSIs) cannot be applied [3]. In many cases, as a MEMS chip, which needs to be controlled by another IC chip, is packaged using silicon or glass cap [4]-[6], it has been difficult to reduce the footprint on the printed circuit board (PCB) and assembly cost. To address these issues, we have developed the hermetic thin-film encapsulation structure fabricated by conventional back end of the line (BEOL) technologies of LSIs as a wafer-level packaging (WLP). In this work, the fabrication processes and mechanical modeling results for thin-film encapsulations and the SiP [7] for MEMS and IC chips are shown for the fabrication of the multi-chip package (MCP).

In this paper, we report In-line wafer level hermetic packages (WLP) for MEMS variable capacitors. The beam structure of MEMS vibrates strongly under decompression. Since this vibration causes RF noise, it is necessary to set the pressure around the beam structure at 40000Pa or greater. Therefore, a structure that carries out a resin seal of the hole for etching the cap of a formed in the sacrificial layer process, at atmospheric pressure (101300Pa) is crucial for what. To prevent moisture permeation inside a cap, the resin was coated with a PECVD SiN layer. The developed packages become a hybrid hermetic encapsulation, which consists of PECVD SiN layers. Moreover, the deformation of the cap by external pressure was reduced using a corrugated cap. The developed package is comparatively large (340x1100µm). Nevertheless, after the 265 o C reflow test (5 times) and -55 o C/125 o C thermal cycle test (20 cycles), no cracks were observed in the packages. Since all of such processes and materials are compatible with the CMOS process, this package has very low cost. We present a summary of several aspects of our development activities in this MEMS variable capacitor packaging technology.

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Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelectromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS / IC dies coupled device.