No abstract

No abstract

This paper reports a thin-film encapsulation technology for wafer level micro-electro-mechanical systems (MEMS) package, using poly-benzo-oxazole (PBO) sacrificial material and plasma enhanced chemical vapor deposited silicon oxide (PECVD SiO) cap layer. This technique, which is applicable for MEMS technologies, saves die size and enables conventional package processes such as dicing, picking, mounting and bonding. Besides the fabrication processes of the thin-film encapsulation, this paper also presents the results of finite element models (FEMs) for the deflection and the mechanical stress of the thin-film caps.Moreover, in order to mount a MEMS chip with the thinfilm capsulations and another integrated circuit (IC) chip that controls a MEMS chip in the same package, we have also developed an epoxy reinforcement technique for protecting the thin-film encapsulations and a topography wafer thinning technique for the MEMS chip. And then the system in package (SiP) for the MEMS and IC chips is fabricated successfully based on the mechanical analysis of the SiP process. IntroductionSince MEMS, such as various sensors and radio frequency (RF) actuators [1], [2], consist of movable parts and need to be operated in vacuum or controlled atmosphere, the conventional package techniques for large-scale integrated circuits (LSIs) cannot be applied [3]. In many cases, as a MEMS chip, which needs to be controlled by another IC chip, is packaged using silicon or glass cap [4]-[6], it has been difficult to reduce the footprint on the printed circuit board (PCB) and assembly cost. To address these issues, we have developed the hermetic thin-film encapsulation structure fabricated by conventional back end of the line (BEOL) technologies of LSIs as a wafer-level packaging (WLP). In this work, the fabrication processes and mechanical modeling results for thin-film encapsulations and the SiP [7] for MEMS and IC chips are shown for the fabrication of the multi-chip package (MCP).

A microsphere/cylinder waveguide resonator for directly coupling a light beam into a waveguide is proposed. To avoid unwanted resonance in the core, a metallic core is used on which a high refractive index waveguide is placed to form a shell structure. The input or output light coupling is realized by using the leaky mode of a specially designed curved waveguide.

This paper describes a comprehensive characterization of a 65 nm, 300" wafer size interconnect technology with SiCOH material (k=2.8). Excellent film properties of SiCOH material and precise process optimization enable the minimization of damaged layer during etching and strip processes. 3D modeling reveals that the k-value of SiCOH material was maintained at its initial value after the integration. Electrical yield, reliability and chip-to-package (CPI) evaluation are also presented. The results were comparable with conventional SiCOH integration scheme.