A 3D packaging technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the socalled SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding. Simulation of the transfer function of FTI wiring indicated a 3 Gbps/pin data transfer capability.

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SUMMARYThe national project of ultrahigh-density electronics SI (system integration) technology was started in 1999 and finalized in March 2004. Many research achievements occurred in various areas, such as three-dimensional integration, optoelectronic composite integration, and optimal connection structure design. Among these, the development of the three-dimensional LSI chip stacking technique is especially important in providing a core for future SiP technology. There are also many intensive studies on this topic in research institutions in various countries. The achievements of research in ASET cover a wide range, from the development of process technology to devices approaching practical models, indicating that the technology is highly mature.

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A 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics.