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This paper deals with the low power design of synchronous finite state machines (FSM) with respect to a given sequence of primary input signals (pattern). We suggest a novel and practical synthesis approach to reduce switching activity by disabling particular self-loops combined with an appropriate state encoding. The required analysis of the FSM behavior regarding to the pattern sequence is performed by an underlying profiling step. The experimental results show that the power can be considerably reduced but the obtained reduction depends decisively on both, the FSM structure as well as the pattern sequence.

In this paper we propose a new state encoding approach for power reduction of digital controllers. We utilize in the encoding procedure two optimization parameters simultaneously: area and register switching rate. The area is approximated by the number of rows in the FSM controller specification. Our approach for power reduction exploits an adapted encoding strategy and provides a proper trade-off regarding both parameters. A couple of experimental results show the practicability of our approach.

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