Abstract

This paper deals with the low power design of synchronous finite state machines (FSM) with respect to a given sequence of primary input signals (pattern). We suggest a novel and practical synthesis approach to reduce switching activity by disabling particular self-loops combined with an appropriate state encoding. The required analysis of the FSM behavior regarding to the pattern sequence is performed by an underlying profiling step. The experimental results show that the power can be considerably reduced but the obtained reduction depends decisively on both, the FSM structure as well as the pattern sequence.

No abstract

No abstract

Designing System-on-a-Chip (SoC) using system-level languages is becoming a standard in industry. However, the non-deterministic semantics of such parallel languages could yield failures that are hard to debug. In this paper, we present a new approach that supports automatic debugging of SoC designs written in SystemC using a method that isolates failure-inducing process schedules.