NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16Gb 4-level NAND flash memory in 43nm CMOS technology. Figure 23.6.1 shows a micrograph of the chip. The pads are placed along one long side for better routing. The chip has 2 planes with 1K blocks per plane, 1M bytes per block and 8K bytes per page. With 66 NAND cells per string the chip area is reduced by about 9.2%. We also use efficient CG driver sets, ground bus on the array, as well as dual-stage driver circuits (DSD) to enable a die size of 9.28×12.96mm 2 (120.27mm 2 ) and realize a 2GB single-chip microSD memory card. Dummy wordlines suppress GIDL and provide better program disturb immunity. To enable voltage scaling while maintaining cost effectiveness, DSD circuits in the I/O achieve 25ns cycle time at 1.8V VCCQ.The NAND flash is composed of memory cells sandwiched by select gates (SG). The select gates between bitlines and NAND strings in unselected blocks are cutoff during read and program operations. Although the transistor length (L) of a memory cell decreases with scaling, it is desirable to maintain L of SG different from L of cell transistors to reduce short channel effects. Consequently, the periodicity of gate pattern breaks down around the SG area as shown in Fig. 23.6.2 [1]. Therefore, it is necessary to consider the electrical effects of SG on two sides of NAND strings [2,3].In 43nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings as shown in Fig. 23.6.3. GIDL causes severe program disturb problems to NAND flash memories [4]. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, V dg , are selected independent of the program inhibit voltage or V pass . However, the dummy WLs lead to chip area increase. Therefore, the NAND string length is changed from 32 cells to 66 (64 + 2 dummy WLs) to reduce the area penalty.NAND flash memories have on-chip charge pump circuits to generate various high voltages, such as program voltage V pgm , V pass , and read voltage V read . These high voltages are selected WL-by-WL in control gate (CG) drive circuits and are routed to row decoders. Since the CG drivers are located in the periphery, 32 CG drivers are needed and 32 high-voltage buses are run to row decoders if a string has 32 cells. Increasing the string length from 32 to 66, requires area for an additional 34 (= 32 + 2 dummy WLs) CG drivers and 34 voltage buses. Furthermore, the row decoders are located on both sides of the memory array to relax wiring pitches, making layout lithography friendly in 43nm technology. Thus, the CG high-voltage buses run from left to right and their area overhead is not negligible. Theref...
