The authors have determined the composition profile within individual Si1−xGex nanoscale islands on Si(001). Samples have been grown by means of liquid phase epitaxy in the Stranski-Krastanov mode. By applying electron energy loss spectroscopy, the intensities of Si K and Ge L edges have been measured to determine the relative atomic concentration of germanium. The quantification of the composition suggests a profile comprising of two regions with different linear concentration gradients.

Extreme variations in surface reflectivity/topography have been observed on silicon wafers with evaporated aluminum metallization following thermal annealing processes. Such topographic variations negatively impacted the performance of wire bonder pattern recognition systems. It was proposed that this variation was attributed to differences in deposition rates during evaporation of the aluminum front metallization. SEM analysis revealed that the topographically rough sites, deemed as normal for this processing sequence, had large numbers of hillocks, while the smooth sites exhibited limited numbers of hillocks after heat treatment. SIMS depth profiling analyses did not indicate that any elemental difference existed between the smooth and the rough sites, although interfacial differences were detected. Specifically, the Al-Si interface for the rough surface was more graded in nature while the Al-Si interface for the smooth surface was more abrupt. TEM analysis of the rough sites revealed that a three-dimensional island growth mechanism prevailed during film growth, resulting in uneven surface development, whereas analysis of the smooth sites showed a columnar grain structure.

This paper investigates Cu segregation and void morphology along AlCu alloy metal lines as a function of resistance change resulting from isothermal DC stressing at 225°C and a current density of J=2×106 A/cm2. The Al-1.5wt.%Cu alloy was deposited via DC magnetron sputtering onto a Si substrate at 525°C with a 1500Å TiW barrier layer. NIST test structures (length = 800µm, thickness = 1.2µm, width = 5 and 10 µm) were utilized in this study. BPSG was used as the insulation layer between Si substrate and conductor. The surface passivation layer was composed of Si3N4/PSG. Various failure criteria were selected to explore the correlation between Cu segregation and void morphology along the metal line and the relative percent resistance change (ΔR/R). The log-normal plots, mean-times-to-failure, and sigmas at each ΔR/R ( -−%, 2%, 5%, 10%, 20%, 100%, 250%) were plotted and listed. The microstructural evolution in terms of void morphology was monitored using SEM. SEM-EDS was used to analyze the Cu concentrations along metal lines tested at various %ΔR criteria.

The p-n junction of a GaAs light emitting diode is fabricated using liquid phase epitaxy (LPE). The junction is grown on a Si doped (~1018/cm3) GaAs substrate. Intermittent yield loss due to forward voltage snapback was observed. Historically, out of specification forward voltage (Vf) parameters have been correlated to abnormalities in the junction formation. Scanning electron (SEM) and optical microscopy of cleaved and stained samples revealed a continuous layer of material approximately 2.5 to 3.0 μm thick at the n-epi/substrate interface. Characterization of a defective wafer via secondary ion mass spectroscopy (SIMS) revealed an elevated concentration of O throughout the region containing the defect. X-ray Photoelectron Spectroscopy (XPS) and Auger Electron Spectroscopy (AES) data taken from a wafer prior to growth of the epi layers did not reveal any unusual oxidation or contamination. Extensive review of the processing data suggested LPE furnace pressure was the obvious source of variability. Processing wafers through the LPE furnace with a slight positive H2 gas pressure has greatly reduced the occurrence of this defect.

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