With lower I/O operating voltage and decreasing noise margin targets, it is imperative that the amount of noise generated on the voltage rails is kept within tight tolerances for high speed signaling. For this a good understanding of the behavioral model of the package and on-die passives is required in addition to the on-die transients generated on the power supply network when I/O's toggle. One of the major challenges is to accurately measure this dynamic power fluctuation (di/dt) for various I/O bit pattern excitation to understand the effectiveness of decoupling capacitors in the power distribution network. This paper discusses the power delivery validation methodology of the processor Front Side Bus (FSB) that allows the user to input a stream of data into the I/O's to measure the power supply noise and the resulting dynamic power fluctuation. A detailed three dimensional model of the package, motherboard was then created and simulated using Speed2K/PowerSI[1] to correlate with measured results.

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The alarming growth of power increase has presented numerous packaging challenges for high performance processors. The average power consumed by a processor is the sum of dynamic and leakage power. The dynamic power is proportional to V^2, while the leakage current (therefore leakage power) is proportional to V^b where V is the voltage and b>1 for modern processes. This means lowering voltage reduces energy consumed per clock cycle but reduces the maximum frequency at which the processor can operate at. Since reducing voltage reduces power faster than it does frequency, integrating more cores into the processor would result in better performance/power efficiency but would generate more memory accesses, driving a need for larger cache and high speed signaling [1]. In addition, the design goal to create unified package pinout for both single core and multicore product flavors adds additional constraint to create a cost effective package solution for both market segments. This paper discusses the design strategy and performance of dual die package to optimize package performance for cost.