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Abstract² Signal Integrity (SI) and Power Integrity (PI) issues caused by on-board Voltage Regulator (VR) interfering always leads to system reliability problem. Prediction of this VR noise is very difficult due to its complexity. This paper addresses a twostep simulation method associated with this issue by identifying radiation source and coupling path. A typical PCB routing is studied and result is correlated with measurement.

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With lower I/O operating voltage and decreasing noise margin targets, it is imperative that the amount of noise generated on the voltage rails is kept within tight tolerances for high speed signaling. For this a good understanding of the behavioral model of the package and on-die passives is required in addition to the on-die transients generated on the power supply network when I/O's toggle. One of the major challenges is to accurately measure this dynamic power fluctuation (di/dt) for various I/O bit pattern excitation to understand the effectiveness of decoupling capacitors in the power distribution network. This paper discusses the power delivery validation methodology of the processor Front Side Bus (FSB) that allows the user to input a stream of data into the I/O's to measure the power supply noise and the resulting dynamic power fluctuation. A detailed three dimensional model of the package, motherboard was then created and simulated using Speed2K/PowerSI[1] to correlate with measured results.

In this paper, a state of the art TDR with a rise time of 9ps was employed in the characterization of multi-layer ball-grid array (BGA) or land-grid array (LGA) packages. The hardware used for 9ps rising time was the Picosecond Pulse Lab’s 4022 Source Enhancement Module that reduces a standard TDR rise time of 35–40ps to 9ps. The high-resolution TDR can clearly indicates a root cause of a multi-layer package signal integrity problem (impedance mismatching) in vertical transitions consisting of vias and planes which cannot be observed with a conventional TDR. In addition, due to its high-resolution, it was observed that the size of characteristic impedance testing transmission lines can be significantly scaled down. For example, a minimum length of 15–20 mm long transmission lines with a standard TDR can be reduced down to 3–4mm long for 9ps TDR. Using the TDR waveforms, reflection loss S11 (dB) was computed using direct convolution method and short-open-load (SOL) calibration method. The resulting (TDR generated) S11 agrees excellently with direct vector network analyzer (VNA) measurements up to 50 GHz which is the highest frequency available with Agilent 8364A.