The continuing growth of complexity in modern ULSI design, combined with sub-nanosecond switching speeds, have made necessary the careful assessment of issues such as interplane capacitance, decoupling capacitor selection and placement, as well as resonance effects in the power distribution network. Toward this objective, various research groups have proposed modeling methodologies based on a two-dimensional approximation of Maxwell's equations in the space between adjacent powerlground planes. In this paper, a solid power/ground plane pair is discretized by a distributed RLCG circuit. The resulting discrete model is used in conjunction with the passive reduced-order modeling algorithm PRIMA for the generation of low order, multi-port macromodels to be incorporated in non-linear circuit simulators such as SPICE. Through a rigorous mathematical and physical investigation of the distributed electromagnetic effects between powerlground planes, reliable estimates for the order of the reduced model are derived for accurate multiport modeling over a given frequency bandwidth. The numerical results show that the generated rules provide the robustness required for the numerical generation of guaranteed-passive, reduced order electrical models for powerlground plane structures of optimum complexity.
In this paper, a state of the art TDR with a rise time of 9ps was employed in the characterization of multi-layer ball-grid array (BGA) or land-grid array (LGA) packages. The hardware used for 9ps rising time was the Picosecond Pulse Lab’s 4022 Source Enhancement Module that reduces a standard TDR rise time of 35–40ps to 9ps. The high-resolution TDR can clearly indicates a root cause of a multi-layer package signal integrity problem (impedance mismatching) in vertical transitions consisting of vias and planes which cannot be observed with a conventional TDR. In addition, due to its high-resolution, it was observed that the size of characteristic impedance testing transmission lines can be significantly scaled down. For example, a minimum length of 15–20 mm long transmission lines with a standard TDR can be reduced down to 3–4mm long for 9ps TDR. Using the TDR waveforms, reflection loss S11 (dB) was computed using direct convolution method and short-open-load (SOL) calibration method. The resulting (TDR generated) S11 agrees excellently with direct vector network analyzer (VNA) measurements up to 50 GHz which is the highest frequency available with Agilent 8364A.
The optimization of high speed channel demands more challenging tasks such as estimating the noise from the interaction between signal nets and power nets, assessing the on-chip Power Delivery Network (PDN) effectiveness, and including the Power Delivery (PD) to signal coupling noise into the channel budget. However, even just identifying what to optimize in high-speed channel is difficult task, and obtaining meaningful parameters including interaction between signal integrity and power integrity is more challenging. The proposed analysis method employs accurate and more effective ways to find controllable parameters to optimize the channel response for the best performance in the high speed channel considering both signal integrity (SI) and power integrity (PI) interactions by utilizing response decomposition in the time domain with worst case pattern consideration.
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