The optimization of high speed channel demands more challenging tasks such as estimating the noise from the interaction between signal nets and power nets, assessing the on-chip Power Delivery Network (PDN) effectiveness, and including the Power Delivery (PD) to signal coupling noise into the channel budget. However, even just identifying what to optimize in high-speed channel is difficult task, and obtaining meaningful parameters including interaction between signal integrity and power integrity is more challenging. The proposed analysis method employs accurate and more effective ways to find controllable parameters to optimize the channel response for the best performance in the high speed channel considering both signal integrity (SI) and power integrity (PI) interactions by utilizing response decomposition in the time domain with worst case pattern consideration.

On-chip PDN consists of power grid and the intentional decap. In this paper, we demonstrate a technique to determine the on-chip PDN model for a chipset. 2D TLM approach can be used up-to several GHz.

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