Controllable parameters identification for high speed channel through signal-power integrity combined analysis

Choi, Myoung Joon; Pandit, Vishram; Ryu, Woong Hwan

doi:10.1109/ectc.2008.4550042

Cited by 5 publications

(1 citation statement)

References 15 publications

(10 reference statements)

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“…Some work has also been done to demonstrate the effect of SSN on signal propagation delays and voltage levels [6][7][8]. In this paper, we present a new methodology of quantifying the impact of SSN on timing and voltage margin by looking at jitter and noise on the signal in terms of PDN impedance.…”

Section: Introductionmentioning

confidence: 99%

Correlation of PDN impedance with jitter and voltage margin for high speed channels

Laddha

Swaminathan

2008

2008 IEEE-EPEP Electrical Performance of Electronic Packaging

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Timing margin (jitter) and voltage margin (noise) are the main bottlenecks in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities such as signal via transitions and plane cutouts is a major source of jitter and noise introduced by the package and the printed circuit boards on the signal interconnects of these channels. In this paper, we present a new methodology to correlate SSN induced signal jitter and noise with the power distribution network (PDN) impedance by studying the exact mechanism of how the PDN impedance affects signal jitter and voltage margin. Further, we validate the analysis by both simulations and measurements and suggest design practices to reduce jitter and noise on the signal.

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Section: Introductionmentioning

confidence: 99%

Correlation of PDN impedance with jitter and voltage margin for high speed channels

Laddha

Swaminathan

2008

2008 IEEE-EPEP Electrical Performance of Electronic Packaging

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A low-cost wire-bonding package design with package built-in three-dimensional distributed matching circuit for over 5Gbps SerDes applications

Oikawa

2009

2009 59th Electronic Components and Technology Conference

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compensates for the impedance difference between the silicon I/O buffer and the system board. A package built-in threedimensional distributed matching circuit technique [1], which had originally been developed for FCBGA, has been extended and adapted for use in the low-cost wire-bonding packages. The matching circuit discussed in this paper consists of only the parasitic R/L/G/C (resistance/ inductance/ conductance/ capacitance) components distributed three-dimensionally along the signal line in the conventional package substrate and bonding wire. Thus there is no need for any additional manufacturing process, which keeps down the production cost of the high-speed consumer devices.Another important aspect of the low-cost wire-bonding package is a signal-power coupling effect [6]. This effect has recently been discussed when analyzing the SSN (simultaneous switching noise) or SSO (simultaneous switching output) of the memory devices such as DDR2/DDR3. However, the effect on the high-speed SerDes signal performance has rarely been discussed.Because of bonding wires and many ground inconsistencies inside the low-cost wire-bonding packages, the signals are easily coupled with the power supply which acts as a non-ideal secondary return path. This secondary return path strongly affects the signal performance in the over 5Gbps region. This paper analyzes the signal-power coupling effect on the high-speed SerDes device for the first time based on the full-wave, full-3D, signal-power-combined electromagnetic analysis. Matching circuit design for the wire-bonding packagesThe fundamental concept of the package built-in threedimensional distributed matching circuit[1] is composed of following two ideas. The first is to control parasitic capacitance nearby signal line distributed three-dimensionally. The second is to control the signal phase difference between the silicon device pin-out and the above controlled parasitic capacitance. In other words, it intentionally uses the phase difference of the traveling electromagnetic wave along the signal line. Therefore, the design is easier for high frequency or high-speed devices which signal phase difference is larger than low frequency or low-speed devices. Fig.1 illustrates an impedance chart for the S-parameters of typical I/O buffer with red line and the transmission line with intermediate capacitance at location L. Because of parasitic capacitance, the impedance of I/O buffer is low and capacitive, which is to be compensated with the signal AbstractThe package built-in three-dimensional distributed matching circuit[1], which had been developed for FCBGA , has been extended to the low-cost wire-bonding packages. The two-metal layer package designed for 6.4Gps SerDes (Serializer-Deserializer) achieved a ~4dB return loss improvement as well as better signal waveform compared to the normal 50-Ohm design. In addition, signal-power coupling effect on the high-speed SerDes device has been analyzed for the first time based on the full-wave, full-3D, signal-powercombined electromagneti...

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A low-cost QFP design for over 8Gbps SerDes applications with inductive return path co-planar waveguide built into the lead frame

Oikawa

2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Controllable parameters identification for high speed channel through signal-power integrity combined analysis

Cited by 5 publications

References 15 publications

Correlation of PDN impedance with jitter and voltage margin for high speed channels

Correlation of PDN impedance with jitter and voltage margin for high speed channels

A low-cost wire-bonding package design with package built-in three-dimensional distributed matching circuit for over 5Gbps SerDes applications

A low-cost QFP design for over 8Gbps SerDes applications with inductive return path co-planar waveguide built into the lead frame

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