A new reduced clock-swing flip-flop, named NAND-type Keeper Hip-Fiop(NDKFF) is proposed. Compared with other conventional reduced clock-swing flip-flops such as HSFF and RCSFF, NDKFF features simple configuration, which does not have additional clock drivers or does not have additional n-a d o r pwells. Compared with the hybrid-latch flip-flop, 52% of the flip-flop power and 64% of the clocking power are saved in the case of 0.25pm CMOS technology. Moreover CLK-to-Q delay is comparable to that of conventional C2MOS-type master-slave flipflop.

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IntroductionIn battery-operated portable communication equipment, it is essential to lower thc operation voltage of the S I , which dissipates most of the power in the system. Due to the small junction capacitance, SO1 device is one of the most promising candidates for realizing high-speed circuits, which can opcrate with the ultra low-voltage of OJV [l]. In a system LSI, level converters are required to match the logic swing of digital LSIs not only to the VO-signal swing [2][3), but also to the required signal swing of analog circuits, such as DIA converters (Fig.1). This is because analog circuits generally opcrate with the higher supply voltage than OJV. Howcvcr, experimental studies have not been done sufficiently for level converters bascd on SO1 technology. This paper describes the performance of high-speed level convertcrs for 0.SV-operating LSIs, fabricated using FDPD-SO1 tcchnolo~. Dual-rail level converterThe level converter wc proposed in the literature [2] was composed of dual-rail charge transfer-gates with a high gain and a CMOS buffcr with high-sped cross-coupled amplificrs (Fig.?). In thc single-rail scheme [4]. the gain of the chargc transfer-gates was very sensitive to the threshold voltage, Vt, and devices with Vt of nearly OV were required for thc O.5V operation. On the othcr hand, the SPICE simulation demonstrated that thc dual-rail scheme realized the high-speed operation with low Vt of around 0.1SV, which is thc same value as used in the 0.5V-opcrating digital LSI. Thus, one of advantages of the dual-rail scheme is the fact that no additional process is required for fabricating devices with Vt of OV. Fig.3 shows cxperimcntal result, of thc dual-rail level convertcr fabricated using 0.35pn-i multi-Vt SO1 CMOS process. Values of Vt wcrc 10.15V and k 0 A V for low-Vt and high-Vt dcvices, respectivcly. In the conversion from the input signal-swing of 0.5V (VddL) to the rangc of 1.0-1.2V (VddH), the conversion time was Cnsec, while it increased with increasing VddH a b v c 1.2V. This is bccause the largc gain of cross-couplcd amplifiers in high VddH rclativcly decreases the drive capability of the input buffcr (Fig.2). In this case, the modcwtc modification of the input buffer-size is needed. Experiments & DiscussionsFig4 shows the chip photograph of the dual-rail lcvcl wnvertcr TEG fabricated using O . Z p PD-SO1 CMOS process. In the case of PD-SO1 deviocs, thc value of Vt can be changed easily by the use of the body bias, without sacrificing thc other transistor charactcristics. A s shown in Fig& the chip was designed to bias Vbn and Vbp to the body of NMOS charge transfer-gate and that of PMOS counterpart, respectively. Shmoo plots are shown in Fig.6 when the tcs? chip operates with low frequency and random input data. Values of Vt in thc body-source voltage of OV werc k0.12V and kO.2OV for samples A and B, respeCtivcly. In thc sample A thc minimum VddL with which the Icvel convertcr functioned was 0.3V, regardless of the body bias ( Fig.6(a)). In the sample B, a slight incrcasc in thc minim...