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In this paper an experimental study of hot carrier degradation and power supply voltage scaling of deep submicron NMOS devices will be presented. Devices were optimized for processes with design rule between 2 pm and 0.17 pm. Charge pumping measurements showed that the lifetime based on interface state generation in the devices was determined only by Ig&/Id and the drain current. It did not depend on gate length, oxide thickness and substrate doping. The lifetime (g,-shifts) of the devices with minimum gate length of different processes fall on a single line in plots of 7 . I d versus Igub/Id. This behaviour can be explained by a different impact of interface damage on transistor parameters of these devices. Light emission spectra and device simulation showed that non-local carrier heating becomes important for devices from deep submicron processes. As a result the power supply voltage is almost independent on design rule for the deep submicron processes (Vdd 5 2.5V).

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