Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27˚C, supply voltage, V DD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.

ABSTRACT:Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today's memory technology. In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. Studied results show that the power dissipation in 7T SRAM cell is least among other configurations because this structure uses a single bit for both read and write operations. This SRAM cell also provides the least power delay product among different studied SRAM configurations. Performance in terms of power dissipation and power delay product are least for 7T SRAM cell among the other SRAM configurations in 90nm CMOS technology.

In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.

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This paper investigates the effect of Static VAR Compensator (SVC) on power system load shedding. SVC is mainly used in power system stability improvement. This paper proposes a new use of SVC to reduce load shedding. An algorithm of Newton Raphson method (NR) to reduce the load shedding for installing SVC in the system is proposed in this paper. 5 bus test system example is used to demonstrate the effect on load shedding. The test results show that the effect of SVC is significant, in this Static VAR compensator (SVC) is incorporated in Newton Raphson method in which Power Flow Solution is a solution of the network under steady state conditions subjected to certain constraints under which the system operates. The power flow solution gives the nodal voltages and phase angles given a set of power injections at buses and specified voltages at a few, the model of SVC i.e. SVC Susceptance model is discussed. It is also shown that the power system losses are decreased after incorporating the SVC in this N-R method. The results are generated for 5-Bus system. By incorporating the SVC the amount of load shedding is reduced to get the voltages in their limits.