Performance Comparison for Different Configurations of SRAM Cells

Sah, Rohit Kumar; Hussain, Inamul; Kumar, M. Vinay

doi:10.15680/ijirset.2015.0401018

Cited by 5 publications

(2 citation statements)

References 7 publications

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“…The programming technology of an FPGA's are generally utilizes SRAM technology [1]. The energy consumption [5] has become a major source due to an considerably increase in an leakage current while we are reducing it's supply voltage and feature size of an SRAM. Instant on operation means, by applying restore and power-up operation the data held in the SRAM will be cleared and that will be placed with the non-volatile data held in the storage cell.…”

Section: Introductionmentioning

confidence: 99%

Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation

Mounica¹,

Ganesh²

2016

IJECE

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Now-a-days, Energy consumption is the major key factor in Memories. By switching the circuit in off mode and with an lower voltages, leads to decrease in an power dissipation of the circuit. Compared to DRAM SRAM'S are mostly used because of their data retaining capability. The major advantage of using SRAM's rather than DRAM'S is that, they are providing fast power-on/off speeds. Hence SRAM's are more preferred over DRAM's for better instant-on operation. Generally SRAM's are classified in to two types namely volatile and non-volatile SRAM's. A non-volatile SRAM enables chip to achieve performance factors and also provides an restore operation which will be enabled by an restore signal to restore the data and also power-up operation is performed. This paper describes about novel NVSRAM circuit which produces better "instant-on operation" compared to previous techniques used in SRAM's. In addition to normal 6T SRAM core, we are using RRAM circuitry (Resistive RAM) to provide better instant-on operation. By comparing the performance factors with 8T2R and 9T2R, 8T1R design performs the best in the Nano meter scale. Thus this paper provides better performances in power, energy, propagation delay and area factors as compared with other designs. Keyword:Energy . Generally SRAM's are preferred than DRAM's because of it's data retaining capability. SRAM performs both volatile and non-volatile operations. In our project we concentrate more on non-volatile SRAM which produces instant on operation [3] . These are designed in two technologies namely transistor technology and resistive technology. In accordingly, resistive technology uses 1R and 2R series. Compared to 2R series 1R produces more non-volatile operation effectively. Hence in this project we are using resistive technology which was often called as Resistive RAM (RRAM). For controlling or flowing of current/voltage through the resistor, we are using one additional transistor which was so called as control transistor. As we know that the transistor will act as a resistor in linear region. The RRAM circuitry which we are using in this paper was act as a "Mermistor" (memory resistor) [4].As the years progressed, expanded thickness 64kb & quicker get to have been accounted for NVSVRAM'S for military applications. The programming technology of an FPGA's are generally utilizes SRAM technology [1]. The energy consumption [5] has become a major source due to an considerably increase in an leakage current while we are reducing it's supply voltage and feature size of an SRAM. Instant

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Section: Introductionmentioning

confidence: 99%

Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation

Mounica¹,

Ganesh²

2016

IJECE

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“…Grounded 7T SRAM cell V. SRAM ARRAY ARCHITECTURE By grouping the SRAM bit bodies, the SRAM array[14] can be created. Hence the SRAM ARRAY structure, in which elements can be stored in such a precise manner to perform the memory functions, as read/write the required data and saves large data by Set the array size by considering the depth and width, whereas N&M and 2N*2m * needed the depth(Number of lines) & width(Number of columns).…”

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confidence: 99%

Strategic Development of Low Power High Speed SRAM Array Design

Raju*,

Satyanarayana,

Ramesh

2019

IJEAT

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Because of the system variations of tiny functional size, enhanced adjustment functions in bits are becoming more and more vital, as technology nodes proceed to scale, primary memory encounter increased energy with output and time impacts such as crosstalk, challenges in consumption and reliability. We suggest a sustainable strategy to error correction in deeply-scale memories in order to tackle increasing failure rates owing to issues. SRAM is frequently used for high-speed memory apps like cache. The SRAM memory layout (SRAM) main parameter is power consumption. SRAM cells are power starving and bad in traditional models. The low-power cell designs for power consumption, delay write and the power retard product has been analyzed in this paper. The most recent upgrade VLSI, primarily in the volatile memory form of the SRAM set built into the PMOS & NMOS series and which is to be included in the cache segment on the CPU and in microcontrollers that are electronically energy-related, and now we have improved the SRAM Array challenges

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