No abstract

The embedding of neural networks in real-time systems performing classification and clustering tasks requires that models be implemented in hardware. A flexible, pipelined associative memory capable of operating in real-time is proposed as a hardware substrate for the emulation of neural fixed-radius clustering and binary classification schemes. This paper points out several important considerations in the development of hardware implementations. As a specific example, it is shown how the ART1 paradigm can be functionally emulated by the limited resolution pipelined architecture, in the absence of full parallelism.

No abstract

No abstract

A design of an adaptive digital circuit based on a neuromorphic (brain-inspired) architecture is proposed. The neuromorphic model employed is a two-layered perceptron, which employs a form of least-mean-square error correction in order to "learn" appropriate internal representations necessary to accomplish the mapping of binary input vectors into desired binary output vectors. The proposed network design differs from the theoretical model in that limited interconnect density between layers and quantized parameter values are employed in order to facilitate VLSI fabrication. Simulation results indicate that the simplified version of the network behaves in ways similar to the fully-connected, floating-point network with approximately the same number of elements in the middle layer. Circuits which are designed with neural-inspired, cellular topology would have the advantage of high fault-tolerance, since information is stored in neural networks in a distributed, rather than a local fashion.