Holes genemted by impact ionization in the channels of InP-based heterostiucture jield-effect transistors can tunnel to the gate electrode and contribute to the parasitic gate current. By inserting pseudomorphic AlAs-spacer layers in order to increase the m[ence-hand discontinuity, the channel-to-gate trunsfer rate of holes can be effectiuely reduced. 0 1996 John Wley & Sons, Inc. INTRODUCTIONThe parasitic gate current through the Schottky gate contact of InP-based InAlAs/InGaAs heterostructure field-effect transistors (HFETs) may cause a deterioration of the off-state breakdown [l], the unilateral gain, and the noise performance [2]. Much effort has been applied to enhancing the Schottky barrier height to reduce the (thermionic) field emission electron current by replacing the InAlAs-barrier layer by a highband-gap material [3, 41. But the main contribution to the gate leakage current at sufficient gate-source and gate-drain breakdown voltages is expected to be holes, tunneling to the gate electrode after generation in the InGaAs channel by impact ionization [S, 61. This hole current can be reduced by increasing the valence-band energy barrier in the spacer layer in order to lower the transfer rate [7, 81.In this study the impact of pseudomorphic AlAs containing spacer layers as hole barriers will be systematically investigated. Based on the correlation between the hole leakage current and the gate-drain breakdown voltage, the hole gate current reduction factor is evaluated as a function of the AlAs-spacer thickness. EXPERIMENTThe heterostructures were grown by solid-source MBE using a Varian Gen I1 apparatus. All samples exhibit the following layer sequence (cf. Figure 1). On top of the buffer, a 20-nrn InGaAs channel layer was grown, followed by a d,-thick AlAs-and a d,-thick InAlAs-spacer layer, an 8-nm InALAs supply layer with a doping level of S X 10l8 cmP3, and a 20-nm-thick InAlAs barrier layer. Finally, a 5-nm undoped and a 5-nm doped (1 X 1019 ~m -~) InGaAs cap layer for ohmic contact formation completes the HFET structure. All layers are lattice matched to InP except the AlAs spacer layer with the thickness d,, varying from 0 to 4.3 nm, as shown in Table 1. In the following the layer structures are indexed by their AlAs-monolayer number (ML). In samples 0-8 ML the spacer was extended by a lattice-matched InAlAs layer of thickness d,. The growth was performed at a V/III-beam equivalent pressure (BEP) ratio of 60 and a growth rate of 0.90 p m / h for InGaAs and of 0.92 p m / h for InAMs, respectively. After thermally cleaning at wafer temperatures up to 545°C measured by a pyrometer, the growth of the samples started at 420°C in order to increase the InAlAs resistivity. A temperature spike up to 540°C near the buffer/channel interface increases the low-field mobilities, as shown in [9]. The deposition of the highly strained AlAs spacer was performed at 440°C to kinetically restrict the migration length of the surface adatoms to inhibit island formation. The temperature changes were performed duri...

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