Automatic document classification has become an important task because of the continually increasing number of text documents with the users have to deal with. The aim of this paper is to develop a non-adaptive meta-classifier for text documents that has an increased classification accuracy. The developed meta-classifier is based on combining some SVM classifiers and a Naïve Bayes classifier. We proposed a new meta-classification method which takes into consideration the corresponding positions and confidence degrees obtained for all the classes. In this work we have tried to find, using Genetic Algorithms, the optimal weighting factors for the values returned by each classifier separately. Consequently, it is possible for the meta-classifier to select as the winner class, a class that is not hierarchized as the first one by any of the compounded classifiers. The experimental results have showed that the classification accuracy can be improved through the proposed method.

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Abstract:The principal aim of this paper is to make a review of main statistical methods for classifying documents that could be easily adapted in the context of Web document retrieval. After presenting the most popular methods of classification we will also define the most accurate indicators for assessment of classifiers performance. Thus we will refer to the recall, precision, fscore, sensitivity and specificity. We will also describe how these indicators can be calculated in the context of Web documents.

Neural Networks are non-linear static o r dynamical systems that learn to solve problems from examples. Most of the learning algorithms require a lot of computing power and, therefore, could benefit from fast dedicate hardware. One of the most common architectures used for this specialpurpose hardware is the Systolic Array [9]. The design and implementation of different Neural Network architectures in Systolic Arrays can be complex, however. This paper shows the manner in which the Hopfield Neural Network can be mapped into a 2 -0 Systolic Array and present an FPGA implementation of the proposed 2 -0 Systolic Array.