Specifications and FPGA implementation of a systolic Hopfield-type associative memory

Abstract

Neural Networks are non-linear static o r dynamical systems that learn to solve problems from examples. Most of the learning algorithms require a lot of computing power and, therefore, could benefit from fast dedicate hardware. One of the most common architectures used for this specialpurpose hardware is the Systolic Array [9]. The design and implementation of different Neural Network architectures in Systolic Arrays can be complex, however. This paper shows the manner in which the Hopfield Neural Network can be mapped into a 2 -0 Systolic Array and present an FPGA implementation of the proposed 2 -0 Systolic Array.

Systolic architecture modeling with architectural petri nets application to a wheelchair neural Control

“…Their combination allows to obtain arrays [7] that can be used in a wide range of applications : Discrete Fourier Transform [8], convolution [9], filtering [10], matrix operations [11].... The regularity of their structures facilitate their hardware, implementation, for instance in FPGAs [12], [13], [14]. The systolic array design depends on the problem to be solved and the constraints that must be taken into account (cells number minimization, data flow simplification...).…”