No abstract

The performance of interconnected rings and oscillators, working as clock distribution networks, is analyzed and compared among several configurations. The use of interconnected 3-inverter rings as globally asynchronous, locally synchronous clock distribution networks is proposed even for chip lengths from 4 to 24 mm. In this approach, modularity and basic cell properties are kept while the power consumption results directly proportional to the number of blocks. Typical 3.3V AMS 0.35µm CMOS N-well process parameters were used for the analysis. Regarding the current area expansion, we show that interconnected rings is a more robust approach than the interconnected oscillators.

The use of interconnected rings approach, as globally asynchronous, locally synchronous clock distribution network, offers good performance regarding scalability, low clock-skew and high-speed clocking. Moreover, they show linear metal-cost growth and the power consumption is directly proportional to number of interconnected rings. In this paper, the performance of interconnected rings, working as clock distribution networks, is analyzed and verified by experimental measurements. Typical 3.3V 0.35µm CMOS N-well AMS process parameters were used for the analysis and chip fabrication. It is shown that interconnected rings are a robust approach under parameters variations.

No abstract

All synchronous systems use a clock distribution network covering a large section of the integrated circuit and handling the fastest frequencies of the device. In this work, the performance of interconnected and coupled ring oscillator arrays working as clock distribution networks is analyzed. The use of interconnected three-delay stages rings are proposed even for chip lengths from 4 to 24 mm. Typical 3.3V AMS 0.35μm CMOS N-well process parameters were used for the design and fabrication. Experimental results of 16 non-expanded and expanded interconnected ring oscillators agree with simulation.I.