Interconnected rings and oscillators as gigahertz clock distribution nets

Maza, Manuel Salim; Aranda, Mónico Linares

doi:10.1145/764813.764819

Cited by 5 publications

(7 citation statements)

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“…Instead of being dictated by a quartz, the frequency of the generated clock signal is determined by the end-to-end delay of the feedback loop. In [51], a regular structure of closed loops of an odd number of inverters is used for distributed clock generation. Similarly, [17,18] employs local tick generation cells, arranged in a two-dimensional grid, with each cell inverting its output signal when its four inputs (from the up, down, left and right neighbor) match the current clock output value.…”

Section: Related Work Vlsi Clock Generationmentioning

confidence: 99%

“…Similarly, [17,18] employs local tick generation cells, arranged in a two-dimensional grid, with each cell inverting its output signal when its four inputs (from the up, down, left and right neighbor) match the current clock output value. Since clock synchronization theory [12] reveals that high connectivity is required for bounded synchronization tightness in the presence of failures, however, the sparsely connected designs proposed in [17,18,51] are not fault-tolerant. Modeling approaches: The theory of asynchronous (clockless) distributed systems -in the absence of failures -has been used in the VLSI community for decades [10]: Research on transition signaling [7,71], delay-insensitivity [16,49], micropipelines [77], etc.…”

Section: Related Work Vlsi Clock Generationmentioning

confidence: 99%

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Reconciling fault-tolerant distributed computing and systems-on-chip

Függer

Schmid

2011

Distrib. Comput.

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Classic distributed computing abstractions do not match well the reality of digital logic gates, which are the elementary building blocks of Systems-on-Chip (SoCs) and other Very Large Scale Integrated (VLSI) circuits: Massively concurrent, continuous computations undermine the concept of sequential processes executing sequences of atomic zerotime computing steps, and very limited computational resources at gate-level make even simple operations prohibitively costly. In this paper, we introduce a modeling and analysis framework based on continuous computations and zerobit message channels, and employ this framework for the correctness & performance analysis of a distributed faulttolerant clocking approach for Systems-on-Chip (SoCs). Starting out from a "classic" distributed Byzantine fault-tolerant tick generation algorithm, we show how to adapt it for direct implementation in clockless digital logic, and rigorously prove its correctness and derive analytic expressions for worst case performance metrics like synchronization precision and clock frequency. Rather than on absolute delay values, both the algorithm's correctness and the achievable synchronization precision depend solely on the ratio of certain path delays. Since these ratios can be mapped directly to placement & routing constraints, there is typically no need This work originates in our DARTS project, which has been a joint effort of Vienna University of Technology and RUAG Space, see http://ti.tuwien.ac.at/darts for details. It has been supported by the Austrian bm:vit FIT-IT project DARTS (809456-SCK/SAI) and the Austrian FWF projects Theta (P17757), PSRTS (P20529) and FATAL (P21694).M. Függer (B) · U. Schmid Technische Universität Wien, Embedded Computing Systems Group (E182/2), Treitlstraße 3, 1040 Vienna, Austria e-mail: fuegger@ecs.tuwien.ac.at U. Schmid e-mail: s@ecs.tuwien.ac.at for changing the algorithm when migrating to a faster implementation technology and/or when using a slightly different layout in an SoC.

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Section: Related Work Vlsi Clock Generationmentioning

confidence: 99%

Section: Related Work Vlsi Clock Generationmentioning

confidence: 99%

Reconciling fault-tolerant distributed computing and systems-on-chip

Függer

Schmid

2011

Distrib. Comput.

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“…This, however, comes at the price of a reduction of clock accurracy and stability. [19,20] presents an alternative approach for generating and distributing GHz clocks. The design relies on the self-oscillation property when interconnecting an odd number of inverters in a ring topology (shown in Figure 2) and achieves high clock frequencies due to its simplicity.…”

Section: Globally Asynchronous Locallymentioning

confidence: 99%

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

Fuchs

Steininger

2011

Journal of Electrical and Computer Engineering

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We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply-properties that are considered highly desirable for future technology nodes.

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“…Instead of being dictated by a quartz, the frequency of the generated clock signal is determined by the end-to-end delay of the feedback loop. In [20], a regular structure of closed loops of an odd number of inverters is used for distributed clock generation. Similarly, [8] employs local tick generation cells, arranged in a two-dimensional grid.…”

Section: Motivationmentioning

confidence: 99%

“…Similarly, [8] employs local tick generation cells, arranged in a two-dimensional grid. Since clock synchronization theory [6] reveals that high connectivity is required for bounded synchronization tightness in presence of failures, however, the sparsely connected designs proposed in [8,20] are not fault-tolerant.…”

Section: Motivationmentioning

confidence: 99%

Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip

Függer

Schmid

Fuchs

et al. 2006

2006 Sixth European Dependable Computing Conference

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MotivationShrinking feature sizes and increasing clock speeds are the most visible signs of the tremendous advances in VLSI design, which will accommodate billions of transistors on a single chip in the near future [12]. This comes at the price of increased system-level complexity, however: With today's deep submicron technology with GHz clock speeds, wiring delays dominate transistor switching delays, and signals cannot traverse the whole die within a single clock cycle any more. Moreover, the reduced voltage swing needed for high clock speeds and low power consumption dramatically increases the adverse effects of single event upsets like α-particle or neutron hits. The resulting increase of the transient failure rate (soft-error rate) [17] and crosstalk sensitivity [23] has raised concerns about the dependabil- ity of future generation VLSI chips [5]. In fact, a modern VLSI chip can no longer be viewed as a monolithic block of synchronous hardware, where all state transitions occur simultaneously. Rather, VLSI chips are nowadays considered as systems of interacting subsystems -the advent of Systems-on-Chip (SoC). Due to the problems listed above, however, SoCs have much in common with the loosely-coupled distributed systems that have been studied by the fault-tolerant distributed algorithms community for decades. This paper explores whether it is possible to utilize some of this research for SoCs and similar VLSI devices.More specifically, in the context of our DARTS-Project (ti.tuwien.ac.at/darts), which is a joint project between Vienna University of Technology and Austrian Aerospace, we will explore an alternative approach (patented in [26]) to synchronous clocking in VLSI chips and PCB-level system designs. As shown in Fig. 1, the idea is to replace the external quartz oscillator and the clock tree, which supplies the clock signal to the different functional units (Fu i ) on a traditional chip, using a GALS-like approach [4]: Every functional unit has attached a dedicated fault-tolerant tick generation block (TS-Alg), which generates the Fu's local clock signal. In contrast to GALS, however, our approach ensures that the local clock signals of different Fu's are closely synchronized to each other. To accomplish this, all TS-Alg blocks communicate with each other over a simple "network" of clock signals (TS-Net). This alternative clock- ing approach has a number of advantages, which makes it particularly promising for certain application domains: First of all, it does not need a quartz oscillator, which is an expensive and sensitive device (shock, vibration, temperature etc.). The generated clock always runs at the maxi-

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Interconnected rings and oscillators as gigahertz clock distribution nets

Cited by 5 publications

References 3 publications

Reconciling fault-tolerant distributed computing and systems-on-chip

Reconciling fault-tolerant distributed computing and systems-on-chip

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip

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