Abstract-The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets -SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.

Fire monitoring systems have usually been based on a single sensor such as smoke or flame. These single sensor systems have been unable to distinguish between true and false presence of fire, such as a smoke from a cigarette which might cause the fire alarm to go off. Consuming energy all day long and being dependent on one sensor that might end with false alert is not efficient and environmentally friendly. We need a system that is efficient not only in sensing fire accurately, but we also need a solution which is smart. In order to improve upon the results of existing single sensor systems, our system uses a combination of three sensors to increase the efficiency. The result from the sensor is then analyzed by a specified rule-set using an AI-based fuzzy logic algorithm; defined in the purposed research, our system detects the presence of fire. Our system is designed to make smart decisions based on the situation; it provides feature updated alerts and hardware controls such as enabling a mechanism to start ventilation if the fire is causing suffocation, and also providing water support to minimize the damage. The purposed system keeps updating the management about the current severity of the environment by continually sensing any change in the environment during fire. The purposed system proved to provide accurate results in the entire 15 test performed around different intensities of a fire situation. The simulation work for the SMDD is done using MATLAB and the result of the experiments is satisfactory.

The exponential function ax is widespread in many fields of science. Its calculation is a complicated issue for Central Processing Units (CPUs) and Graphics Processing Units (GPUs), as well as for specialised Digital Signal Processing (DSP) processors, such as Intelligent Processor Units (IPUs), for the needs of neural networks. This article presents some simple and accurate exponential function calculation algorithms in half, single, and double precision that can be prototyped in Field-Programmable Gate Arrays (FPGAs). It should be noted that, for the approximation, the use of effective polynomials of the first degree was proposed in most cases. The characteristic feature of such algorithms is that they only contain fast ‘bithack’ operations (‘bit manipulation technique’) and Floating-Point (FP) addition, multiplication, and (if necessary) Fused Multiply-Add (FMA) operations. We published an article on algorithms for this class of function recently, but the focus was on the use of approximations of second-degree polynomials and higher, requiring two multiplications and two additions or more, which poses some complications in FPGA implementation. This article considers algorithms based on piecewise linear approximation, with one multiplication and one addition. Such algorithms of low complexity provide decent accuracy and speed, sufficient for practical applications such as accelerators for neural networks, power electronics, machine learning, computer vision, and intelligent robotic systems. These are FP-oriented algorithms; therefore, we briefly describe the characteristic parameters of such numbers.

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

No abstract