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The development of vertical 3D NAND technology over the past 5 years has been accelerated by the parallel development of metrology techniques capable of characterizing these device stacks. Current trends point toward a continuous scaling of dimensions along the z-axis, involving a critical etch step with aspect ratios of ~50:1. These high aspect ratio process steps present both fabrication and metrology challenges where the channel holes can bend, bow, and pinch off throughout the stack. Work presented herein demonstrates the capability of an automated workflow developed using the Thermo Scientific™ Helios™ G4 HXe DualBeam™ platform. The workflow iteratively exposes desired layers within the NAND stack, collects high resolution SEM images, and performs metrology to enable statistical analysis of trends as a function of depth within the stack. Results will be presented from 3 sites in an automatically delayered 72-layer 3D NAND die. Automated SEM metrology was performed every 10 layers, capturing more than 6000 devices. Over 19000 measurements were made on imaged devices yielding assessment of statistically significant trends in the planar cell area, eccentricity, and position of the bits as a function of depth.

This is an Accepted Manuscript for the Microscopy and Microanalysis 2020 Proceedings. This version may be subject to change during the production process.

Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.

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