Because of mask cost reduction, electron beam direct write (EBDW) is implemented for special applications such as rapid prototyping or small volume production in semiconductor industry. One of the most promising applications for EBDW is design verification by means of metal fix. Due to write time constrains, Mix & Match solutions have to be developed at smaller nodes. This study reports on several Mix and Match processes for the integration of E-Beam lithography into the optical litho process flow of Qimonda's 70 nm and 58 nm DRAM nodes. Different metal layers have been patterned in part with DUV litho followed by E-Beam litho using a 50 kV Vistec SB3050 shaped electron beam direct writer. All hardmask patterns were then simultaneously transferred into the DRAM stack. After full chip processing a yield study comprising electrical device characterization and defect investigation was performed. We show detailed results including CD and OVL as well as improvements of the alignment mark recognition. The yield of the E-Beam processed chips was found to be within the range of wafer-to-wafer fluctuation of the POR hardware. We also report on metal fix by electrical cutting of selected diodes in large chip scales which usually cannot be accessed with FIB methods. In summary, we show the capability of EBDW for quick and flexible design verification

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Line edge roughness (LER) and line width roughness (LWR) have raised questions and concerns as current lithography techniques reduce critical dimensions (CD) below 50 nm. There are few applications of controlled variation of LER and LWR, even among those which use electron beam direct writing (EBDW), although it is highly desirable to test the influence of systematical variation of LER and LWR on actual semiconductor devices. To get a clear understanding how and what the LERs and LWRs are influencing in EBDW, we have designed and fabricated transistor gates with programmed LER and LWR using EBDW and observed those based on CD-SEM metrology. The obtained results including calculated power spectrum density (PSD) shows the capability of EBDW to control the LER/LWR. Further, the influence of edge/width roughness in EBDW on device characteristics is reviewed and it gives how the effect of LWR/LER translates to device performance in DRAM process flow. It is found that the con trol of LWR is more important than that of LER for future lithography developments

Process improvements attributed to the use of bottom anti-reflective coatings (B.A.R.C.s) are well documented. As our experience with these materials improves, so does our understanding of additional optimization. Recent supplier experiments suggest an increase in the thickness of AZ® BARLi (bottom anti-reflective layer i-line) solution to reduce photoresist swing curve ratios. Also, changes in thin film stack on common substrates can adversely affect the degree of photoresist reflective notching. It is therefore of extreme importance to determine optimum thickness(es) of a B.A.R.C. material to ensure maximum process potential. We will document several process effects in the conversion of a SRAM test device (0.38 -O.45jtm) from a 650A to a 2000A BARLiTM fi thickness using conventional i-line photolithography.Critical dimension (CD) uniformity and depth of focus (DOF) are evaluated. Defect density between the two processes are compared before and after etch employing optical metrology and electrical test structures. Sensitivity of overlay as a function of BARLiTM fip thickness is investigated as well.

Plasma etch behavior is often explained in terms of "physical" and "chemical" components: both critically related to surface temperatures generated during plasma etching. In an attempt to measure the chemical etch rate component, a specially prepared, 300mm autonomous temperature sensor wafer was used to simultaneously record dynamic surface temperature during plasma etching of photo resist coated and bare silicon surfaces. Data for N 2 / H 2 , Ar / O 2 , O 2 and Cl 2 etching chemistries were then compared with measured resist etch rates and RF sensor wafer data. Although insulation of the temperature sensors from the plasma by the 3 micron resist coating prevented calculation of the etch rate chemical component, the capability of this methodology with resist coatings < 500nm was shown. In addition the use of both RF and temperature sensor wafers to quickly identify and correct semiconductor etch process development issues related to isotropic etch non-uniformity was shown.