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-A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling. I. INTRODUCTIONA challenge for continued SRAM scaling is threshold voltage (V T ) mismatch due to process-induced variations [1], which degrades the minimum operating voltage (V min ) of an SRAM array [2]. To address this challenge, an improved transistor design that provides for reduced short-channel effects (i.e., improved gate control over the channel potential) is required. The quasi-planar tri-gate bulk MOSFET [3] is an example of such a design; it utilizes a gate electrode that is physically wrapped around the top portion of the channel region to provide for greater capacitive coupling between the gate and the channel region [4]. In this work, a timed etch in dilute hydrofluoric (HF) acid solution is used to recess the isolation oxide prior to gate-stack formation, to form quasiplanar bulk MOSFETs using an otherwise conventional fabrication process flow.Improvements in transistor performance and SRAM yield are demonstrated in an early 28nm CMOS technology. The benefits of quasi-planar bulk MOSFET technology for voltage and area scaling are then assessed using three-dimensional (3-D) device simulations with atomistic doping profiles and analytical modeling to estimate 6T-SRAM cell yield for 22nm CMOS technology.

This work describes the fabrication of a trench junctionless field-effect transistor (JL-FET) with ultra-thin channel thickness, by using the dry etching process. Experimental results confirm the excellent performance of the trench JL-FET with nanowires (NWs) at a subthreshold swing (SS) of 109 mV/dec., an I ON /I OFF ratio of 10 7 A/A, and a low drain-induced barrier lowering (DIBL) value of 5 mV/V. Moreover, the trench JL-FET can further increase the device I ON /I OFF ratio, and SS. Importantly, owing to its excellent device characteristics and simple fabrication, the trench JL-FET is highly promising for use in advanced three-dimensional (3-D) stacked ICs applications.