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This paper presents a SAR ADC that literally obviates the need for a reference supply. The reference (charge) of the DAC is instead passively recovered from the residual input common mode signal after each conversion. Such a fully-passive DAC is proved to consume no switching-energy in silicon, and the ADC is able to sustain an SNDR of 47dB with only one supply even if the supply voltage varies from 1V to 0.6V. Implemented in the 0.18-µm CMOS process, the ADC dissipates a linearlyscalable dynamic power of 20.5 to 0.77 µW at a speed from 1.5 MS/s to 0.13 MS/s. As no power rail is connected to the DAC, the PSMR is improved by 59dB as compared to conventional designs. In addition, the PSRR is 61.5 dB when a sinusoidal fluctuation of 300 mVpp is imposed on the single 1-V supply. Without the need for a reference supply or a supply regulator, the proposed ADC is able to share the same supply with digital systems while achieving energy-efficient data conversion regardless of the supply noise.