This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 2% error on average.

Future experiments at the new accelerator facility FAIR (Facility for Antiproton and Ion Research) for the research with ion and anti-proton beams require new developments of front-end electronics to tolerate high data rate. We have developed a PCIe card and front-end cards equipped with the small form-factor pluggable (SFP) transceivers for the data transfer via optical fiber. A new protocol has been designed and implemented on the FPGAs in order to provide communication between the PCIe card and the front-end cards. The standard data acquisition (DAQ) system at GSI, multi-branch system (MBS), has been upgraded to support the PCIe cards and is working stably with the data transfer rate up to 180 Mbytes per second.

A single-chip H.264/MPEG-4 audiovisual LSI for mobile applications including terrestrial digital broadcasting systems such as ISDB-T and DVB-H with a module-wise dynamic voltage/frequency scaling architecture is fabricated in a 90nm 6M CMOS technology. This LSI operates even during the voltage/frequency transition, so there is no performance overhead. Voltage/frequency scaling is realized by a dynamic deskewing system and an on-chip voltage regulator with slew rate control. Figure 7.3.1 shows a micrograph of the chip equipped with four optimally configured RISC processors, dedicated hardware accelerators for specific signal processing, 32Mb embedded DRAM and interfaces for camera, display, audio and network streaming for mobile multimedia applications. The power consumed when decoding QVGA (320x240) H.264 baseline profile level 1.2 video streams at 15frames/s and MPEG-4 AAC LC is only 90mW. The chip features are summarized Fig. 7.3.2.H.264 and MPEG-4 standards play essential roles in the field of mobile multimedia. H.264 is a video compression standard adopted for terrestrial digital broadcasting. Demands for larger image size, higher frame rate and higher image quality are ever increasing. These demands require larger memory capacity and higher operating frequency, both resulting in higher power consumption, which is unacceptable for battery-powered mobile equipments. The LSI described in this paper decodes CIF (352x288) H.264 baseline profile at level 2, or encodes VGA (640x480) MPEG-4 SP @L4a video stream at 30 frames/s while encoding/decoding audio/speech streams and multiplexing/demultiplexing them at 180MHz. Figure 7.3.3 shows the block diagram of the chip.There are four major modules: video frontend, video backend, audio/speech and multiplexer/demultiplexer. Each of the modules consists of an optimally configured 32b media-embedded processor (MeP) core [1] and dedicated hardware accelerators for its specific operation. These modules, peripheral interface units for camera, display, mic/speaker, network, etc. and embedded DRAM are connected via a 64b main bus. As for voltage and frequency, this chip slows down the audio module independently from the rest of the chip. The audio module is decoupled by a voltage/frequency socket from the main bus and an on-chip voltage regulator and a dynamic deskewing system (DDS) for the dynamic voltage/frequency scaling.H.264, compared to previous video standards, requires very high programmability so it is very difficult to implement in dedicated hardware accelerators. By studying data processing procedures, elementary processes, are allocated to the processor core or the hardware accelerators, including a context adaptive variable length decoder. Cooperation between the processor core and dedicated hardware accelerators have successfully reduced a large amount of operation time and power consumption without losing the programmability necessary for H.264. Traditional power reducing techniques such as embedded DRAM, clock gating and gated I/O are implemented as in previous w...

A 60-year-old woman was diagnosed with metastatic pulmonary adenocarcinoma (c-stage IV) with an L858R point mutation in the gene encoding epidermal growth factor receptor (EGFR). Serum amylase levels were elevated (1,531 IU/L) with the salivary-type enzyme dominating. First-line chemotherapy using carboplatin plus paclitaxel reduced serum amylase levels, although second-line gefitinib eventually failed to control tumor growth and hyperamylasemia after 4.5 months of treatment. The cancer cells harbored a positive EGFR mutation and secreted amylase. The number of amylase-producing cancer cells and the immunochemical staining intensity for amylase were significantly reduced after gefitinib treatment. This was a rare case of a lung cancer that expressed amylase and harbored a positive EGFR mutation.

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