This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 2% error on average.

The Belle II detector is designed for a high luminosity upgrade of the Belle detector and the KEKB accelerator at High Energy Accelerator Research Organization (KEK), Japan, to study flavor physics. A design luminosity is about 40 times higher than the KEKB, 8xl0 35 cm-2 sl • The number of readout channels of the drift chamber is 14392 chs. In order to reduce the number of cables between the readout electronics and an electronics hut, the readout electronics is designed to locate at near an end plate of the chamber. The electronics consists of 300 modules having four interface cables: system interfaces, a trigger system interface, and a data acquisition system interface. We tested the electronics with a test detector and have confirmed that the test results meet the requirements from the Belle II experiment.

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