Gate delay estimation in STA under dynamic power supply noise

Abstract

This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 2% error on average.

Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise

“…Current density in a chip has been increasing due to increase in operating frequency and power consumption. Moreover, lowering supply voltage with technology scaling, over-drive voltage (V dd -V th ) is decreasing, which results in higher sensitivity of gate delay to power supply voltage [1]. On the other hand, [2] predicts that PG noise level is nearly constant despite lowering power supply voltage.…”

“…[3] classified the delay variation due to power noise into two categories and carefully calculates the equivalent DC voltage for rise/fall transition to reproduce the stage delay decrease as well as the stage delay increase. Then, [1] improved [3] to overcome inaccuracy originating from higher nonlinearity and sensitivity unique to advanced technology, and shows that the stage delay fluctuations can be estimated well within few percent errors.…”

“…Reference [1] presents a gate delay estimation method taking into account given dynamic noise waveforms. The method derives an equivalent DC voltage V dd_eq that makes the gate delay at V dd_eq equal to the actual gate delay under the dynamic noise, and then compute the gate delay using V dd_eq .…”

“…Several gate delay estimation methods considering a given noise waveform have been proposed to capture the impact of dynamic noise behavior on timing [1][3] [4]. These methods assign equivalent DC voltage to each instance by averaging the noise within a time interval of interest to eliminate dynamic behavior.…”

“…We first investigate their tendencies under dynamic voltage drop and show that the setup time becomes optimistic while the hold time constraint becomes pessimistic under the noise. We then propose an estimation procedure of the setup time and clock-to-Q delay under the dynamic noise on the basis of [1], and evaluate the estimation accuracy. …”