We have evaluated the thermal conductivity of Si/SiGe superlattice films by theoretical analysis and experiment. In experiments, the ultrahigh vacuum chemical vapor deposition is employed to form the Si/ Si 0.71 Ge 0.29 and Si/ Si 0.8 Ge 0.2 superlattice films. The cross-plane thermal conductivities of these superlattice films are measured based on the 3 method. In the theoretical analysis, the phonon transport in Si/ Si 1−x Ge x superlattice film is explored by solving the phonon Boltzmann transport equation. The dependence of the thermal conductivity of the Si/ Si 1−x Ge x superlattice films on the superlattice period, the ratio of layer thicknesses, and the interface roughness is of interest. The calculations show that when the layer thickness is on the order of one percentage of the mean free path or even thinner, the phonons encounter few intrinsic scatterings and consequently concentrate in the directions having high transmissivities. Nonlinear temperature distributions are observed near the interfaces, arising from the size confinement effect and resulting in a slight increase in the film thermal resistances. The interface resistance due to the interface scattering/ roughness, which is nearly independent of the film thickness, nonetheless dominates the effective thermal conductivity, especially when the superlattice period is small. Finally the experimental measurements agree with the theoretical predictions if the specular fraction associated with the interface is properly taken.

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In this study, we used simulation technique to analyze the thermal behaviors and investigate the thermal issues of a designed system in package (SiP) for network system application that based on a three dimensional integrated circuit (3D IC) structure. The 3D IC SiP has an interposer which with regularly embedded through-silicon vias (TSVs); there are one CPU chip and two DRAM chips planted on the top side and bottom side of the interposer, respectively. The interposer with chips is bonded on a BT substrate; the BT substrate is bonded on a PCB; and a metallic heat spreader is placed on and glued to the CPU chip's back-side. Because a 3D IC SiP with TSVs is so complicate for modeling and very difficult for meshing, this study attempted to use the equivalent models of embedded TSV, bump/solder bond and metallic trace to simplify a detail 3D IC model. We introduced a slice model, that four stacked chips on an interposer and each chip has two heaters and TSVs, to verify the accuracy and feasibility of the equivalent model by comparing to the detail model, the results of both models show that they are in a good agreement. By using the equivalent model to simulate the studied 3D IC integrated SiP; we found the CPU temperature would be dominated by the cooling capability of a thermal module that attached on the heat spreader. As for the DRAM chips that underneath the interposer, it is inevitable to have a quite high temperature due to the temperature superposition effect and an obstructed heat flow path. In fact, the severely high temperature of the chips under an interposer should be the main thermal issue for such a 3D IC SiP because there is no easy thermal solution for these chips.