Combined with partial dynamic threshold MOSFET connection scheme, a high density 7T subthreshold SRAM bitcell operating at supply voltage of 200 mV is proposed in this paper. Dual write and single read ensures high read static noise margin of the SRAM bitcell without expense of writability degradation. The 7T SRAM exhibits robust efficiency, making the design less vulnerable to process variation. Compared to the referenced 6T and the 8T SRAM bitcell, the proposed bitcell has four aspects of improvement: (1) 5.1% and 6.1% larger hold margin, (2) 80.6% and 85.5% of standard deviation, (3) 50% and 18% reduction of area (at 200 mV), and (4) 16X and 32X bitcells per bitline. To our best knowledge, the area penalty of proposed SRAM is the smallest with robustness and functionality of subthreshold SRAM achieved.

The SRAM applied to dynamic voltage scaling systems has a problem that the differential voltage of the bitlines (ΔVBL) increases as the supply voltage rises with the conventional replica bitlines technique, and the increased ΔVBL degrades the SRAM performance and dissipates more power. In this paper, a programmable replica bitlines technique is presented to resolve the problem. With the new technique we acquired bitline discharge time reduction up to 25.3% at the cost of 0.6% area penalty in a 16Kb SRAM. The 16Kb SRAM test chip is fabricated by using 65nm low leakage technology. Testing results show that the maximum operational frequency of the SRAM is improved from 4.3% to 9.5% under the voltage range of 0.8V~1.4V comparing with the conventional one. The operating frequency of the SRAM with proposed technique is from 440MHz at 0.8V to 1.62GHz at1.4V.