A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme

Abstract

Combined with partial dynamic threshold MOSFET connection scheme, a high density 7T subthreshold SRAM bitcell operating at supply voltage of 200 mV is proposed in this paper. Dual write and single read ensures high read static noise margin of the SRAM bitcell without expense of writability degradation. The 7T SRAM exhibits robust efficiency, making the design less vulnerable to process variation. Compared to the referenced 6T and the 8T SRAM bitcell, the proposed bitcell has four aspects of improvement: (1) 5.1% and 6.1% larger hold margin, (2) 80.6% and 85.5% of standard deviation, (3) 50% and 18% reduction of area (at 200 mV), and (4) 16X and 32X bitcells per bitline. To our best knowledge, the area penalty of proposed SRAM is the smallest with robustness and functionality of subthreshold SRAM achieved.

A data aware 9T static random access memory cell for low power consumption and improved stability

“…Power dissipation becomes one of the most important factors that affect the circuit performance as the device scale down in deep sub micron region. Many researchers have proposed subthreshold SRAM cells [7][8][9][10][11][12][13] as a possible design option to reduce power consumption. For sub-100-nm technologies, the active power consumption in SRAM cell cannot be simply reduced by reducing the power supply because it increases the sensitivity of SRAM to various process parameters and temperature.…”