Software-implemented hardware fault tolerance techniques can be used as a cost-effective alternative to hardware-implemented techniques to enhance the resilience of microprocessor systems. As with many of these softwareimplemented techniques, our recently developed low-level reexecution-based DETECTOR strategy suffers from high execution time overhead. Recently, error detection techniques using the concept of selective hardening to reduce this execution time overhead have been researched. Based on this concept, this paper proposes a selective implementation of DETECTOR called S-DETECTOR, which only protects a part of the target program based on its most vulnerable registers. Experimental results show that a considerable overhead reduction is obtained with a minor drop in fault coverage.