Nowadays, embedded systems are widely used both in general-purpose as well as in safety-critical applications. Due to technological advances, these embedded systems can operate on extremely small footprints and low voltages. This, however, makes them more susceptible to external disturbances such as electromagnetic interference. These disturbances can cause single event upsets, a bit being flipped inside the microcontroller, which in turn can result in unexpected and unpredictable behavior of the system due to control flow errors or data flow errors. Many software-implemented control flow and data flow error detection techniques have been examined in the past. However, these techniques often require a large amount of devoted CPU registers to work correctly. Not every system is able to devote a large portion of its registers to an error detection technique. This paper proposes DETECTOR: a new low-level re-execution based technique protecting against both data flow and control flow errors, while using only three CPU registers. The experimental results presented in this paper are promising, showing that DETECTOR is able to significantly increase the reliability of the system.

External disturbances such as alpha particles, electromagnetic interference, or malicious external attackers can cause erroneous bit-flips in the hardware of modern embedded systems. A broad range of software-implemented error detection techniques have been presented in the past to safeguard embedded systems against these disturbances. Two well-known state-of-the-art techniques are SWIFT and SWIFT-R. However, since those solutions must be implemented in low-level code, such as assembly language, implementing them can be time-consuming and error-prone. To solve this issue, this paper describes a GCC compiler extension in the form of a plugin that can integrate the data flow error detection of SWIFT and SWIFT-R to any ARMv7-M program. We verify that the compiler implements the techniques correctly by performing fault injection campaigns on various case studies.

Software-implemented hardware fault tolerance techniques can be used as a cost-effective alternative to hardware-implemented techniques to enhance the resilience of microprocessor systems. As with many of these softwareimplemented techniques, our recently developed low-level reexecution-based DETECTOR strategy suffers from high execution time overhead. Recently, error detection techniques using the concept of selective hardening to reduce this execution time overhead have been researched. Based on this concept, this paper proposes a selective implementation of DETECTOR called S-DETECTOR, which only protects a part of the target program based on its most vulnerable registers. Experimental results show that a considerable overhead reduction is obtained with a minor drop in fault coverage.