In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field-effect transistors (FETs) with Hf 0.5 Zr 0.5 O 2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.

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<p>In this study, we present CIMulator, a simulation platform for crossbar arrays based on synaptic element types such as resistive random access memory (RRAM), ferroelectric field-effect transistor (FeFET), and phase change memory (PCM) devices. We have developed a custom-made synapse model for FeFET and adopted non-linear weight update expressions for RRAM and PCM to study the non-ideal behaviors and device variations extensively. To reduce the required distinguishable conductance levels of the devices, advanced methods such as the accumulated weight update method and novel architectures such as 1D1S were employed, resulting in great results with reduced efforts. However, this methodology may not be advantageous for all synaptic devices and at all times. Therefore, we present the most viable neural network solution based on device characteristics. Our results demonstrate that the proposed simulation platform can effectively model analog synaptic devices and provide insight into their non-ideal behaviors and device variations, contributing to the development of efficient and highperformance neuromorphic computing systems.</p>

<p>In this study, we present CIMulator, a simulation platform for crossbar arrays based on synaptic element types such as resistive random access memory (RRAM), ferroelectric field-effect transistor (FeFET), and phase change memory (PCM) devices. We have developed a custom-made synapse model for FeFET and adopted non-linear weight update expressions for RRAM and PCM to study the non-ideal behaviors and device variations extensively. To reduce the required distinguishable conductance levels of the devices, advanced methods such as the accumulated weight update method and novel architectures such as 1D1S were employed, resulting in great results with reduced efforts. However, this methodology may not be advantageous for all synaptic devices and at all times. Therefore, we present the most viable neural network solution based on device characteristics. Our results demonstrate that the proposed simulation platform can effectively model analog synaptic devices and provide insight into their non-ideal behaviors and device variations, contributing to the development of efficient and highperformance neuromorphic computing systems.</p>